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Anthony A Immorlica

from Mont Vernon, NH
Age ~78
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Also known as:
Tony A Immorlica, Annette G Immorlica, Annette G Inmorlica
Phone and address:
6 Purgatory Rd, Mount Vernon, NH 03057
(603) 673-9629
Related to:
Nicole S Immorlica, 45
Connected to:
Anita S Imms, 65Daniel J Imms, 62Ayo ImoruMichele F Imossi, 60Tamara T Imoto, 54Angela Imparato, 40Bridget M Imparato, 60Frank Imparo, 56Rachel S Imper, 76Frances A Imperato, 74

Anthony Immorlica Phones & Addresses

  • 6 Purgatory Rd, Mont Vernon, NH 03057 (603) 673-9629 (603) 673-9639
  • Cold Spring, NY
  • 12 Penn St, Fishkill, NY 12524 (845) 265-3472
  • Manlius, NY
  • Syracuse, NY
  • Irvine, CA
  • 6 Purgatory Rd, Mont Vernon, NH 03057 (603) 673-9629

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Graduate or professional degree

Professional Records

License Records

Anthony Aloysius Immorlica

Address:
6 Purgatory Rd, Mont Vernon, NH 03057
License #:
A2845428
Category:
Airmen

Publications

Us Patents

Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates

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US Patent:
8304332, Nov 6, 2012
Filed:
Jun 1, 2011
Appl. No.:
13/150359
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 21/28
US Classification:
438582, 438571, 257E2124
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates

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US Patent:
20100163936, Jul 1, 2010
Filed:
Aug 31, 2007
Appl. No.:
12/086854
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-Chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
International Classification:
H01L 29/812
H01L 21/283
US Classification:
257284, 438602, 257E21159, 257E29321
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates

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US Patent:
20120205726, Aug 16, 2012
Filed:
Jun 1, 2011
Appl. No.:
13/150352
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 29/812
US Classification:
257280, 257E29317
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

Method And Design Of An Rf Thru-Via Interconnect

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US Patent:
20130341644, Dec 26, 2013
Filed:
Jul 18, 2012
Appl. No.:
13/879696
Inventors:
Pane-chane Chao - Nashua NH, US
Bernard J. Schmanski - Merrimack NH, US
Anthony A. Immorlica - Mont Vernon NH, US
Kanin Chu - Nashua NH, US
Dong Xu - Nashua NH, US
Sue May Jessup - Windham NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 23/373
US Classification:
257 77, 257 76, 438584
Abstract:
In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Wafer Level Integration And Testing

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US Patent:
53669061, Nov 22, 1994
Filed:
Oct 16, 1992
Appl. No.:
7/962000
Inventors:
Robert J. Wojnarowski - Ballston Lake NY
Constantine A. Neugebauer - Schenectady NY
Wolfgang Daum - Schenectady NY
Bernard Gorowitz - Clifton Park NY
Eric J. Wildi - Niskayuna NY
Michael Gdula - Knox NY
Stanton E. Weaver - Northville NY
Anthony A. Immorlica - Manlius NY
Assignee:
Martin Marietta Corporation - Philadelphia PA
International Classification:
H01L 2166
G01R 3126
US Classification:
437 8
Abstract:
In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

Optically Patterned Rf Shield For An Integrated Circuit Chip For Analog And/Or Digital Operation At Microwave Frequencies

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US Patent:
51517698, Sep 29, 1992
Filed:
Apr 4, 1991
Appl. No.:
7/680376
Inventors:
Anthony A. Immorlica - Manlius NY
Robert F. Chase - Fayetteville NY
Assignee:
General Electric Company - Syracuse NY
International Classification:
H01L 2940
H01L 2302
H01L 2316
H01L 2504
US Classification:
357 53
Abstract:
The invention relates to the provision of an RF shield for an individual or a collection of integrated circuit chips in a module containing a plurality of hybrid interconnected chips generating interfering RF fields that would interfere with operation of that chip if unshielded. The chips in the module may function in the analog and/or digital mode. The RF shield comprises separate metallizations under and over the chip, the two metallizations being interconnected by a line of discrete electrically conductive vias forming cage-like sides to complete an electrically conductive enclosure about the chip. The vias are spaced closely enough to prevent the escape or entry of RF waves at the frequencies of interest. The RF shield is advantageously fabricated using metallizations and vias that are optically patterned by the same process steps used to effect hybrid interconnection of the chips.

Off-Chip Impedance Matching Utilizing A Dielectric Element And High Density Interconnect Technology

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US Patent:
55593631, Sep 24, 1996
Filed:
Jun 6, 1995
Appl. No.:
8/469706
Inventors:
Anthony A. Immorlica - Manlius NY
Assignee:
Martin Marietta Corporation - Bethesda MD
International Classification:
H01L 2940
H01L 2334
US Classification:
257664
Abstract:
A high-frequency, high-power, semiconductor device chip is impedance matched to an off-chip impedance by a matching network including a dielectric element located on a substrate ground plane portion adjacent to the device to be matched. A thin film dielectric layer is formed over the dielectric element, the semiconductor device and the surrounding substrate. A patterned metal matching circuit is disposed over the dielectric layer and is in electrical contact with an electrode of the high-frequency, high-power, semiconductor device. An impedance matching network is formed by the patterned metal circuit, the dielectric element, the dielectric layer and the underlying grounded substrate. The matching characteristics of the network can be tailored by selecting suitable dielectric materials for the dielectric element and by altering design of the patterned metal circuit. This fabrication of a high-density-interconnect (HDI) structure provides a method for altering the patterned metal circuit by laser lithography, such that a matching circuit can be uniquely tailored to the individual circuit during manufacture, and eliminating the need to mechanically tune the circuit or stock various versions of metallized substrates.
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Anthony A Immorlica from Mont Vernon, NH, age ~78 Get Report