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Donald Schropp Phones & Addresses

  • Sunnyvale, CA
  • 835 Asbury St, San Jose, CA 95126 (408) 998-1911
  • 945 University Ave, San Jose, CA 95126 (408) 998-1911
  • Santa Clara, CA
  • Austin, TX
  • 13837 Steprock Canyon Pl, Tucson, AZ 85737
  • Oro Valley, AZ
  • River Oaks, TX

Work

Company: Synaptics 2011 to 2013 Position: Senior staff system architect

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Yale University 1982 to 1988 Specialities: Physics

Skills

Sensors • Engineering

Industries

Research

Resumes

Resumes

Donald Schropp Photo 1

Donald Schropp

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Location:
835 Asbury St, San Jose, CA 95126
Industry:
Research
Work:
Synaptics 2011 - 2013
Senior Staff System Architect

Heatgenie 2009 - 2011
Senior Scientist

Applied Nanotech, Inc. 2005 - 2008
Senior Scientist

Candescent Technologies 1996 - 2002
Senior Scientist
Education:
Yale University 1982 - 1988
Doctorates, Doctor of Philosophy, Physics
University of Washington 1978 - 1982
Bachelors, Bachelor of Science, Physics
Skills:
Sensors
Engineering

Publications

Us Patents

Voltage Ratio Regulator Circuit For A Spacer Electrode Of A Flat Panel Display Screen

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US Patent:
60519371, Apr 18, 2000
Filed:
May 29, 1998
Appl. No.:
9/087268
Inventors:
James C. Dunphy - San Jose CA
Donald R. Schropp - San Jose CA
Assignee:
Candescent Technologies Corporation - San Jose CA
International Classification:
G05F 100
US Classification:
315291
Abstract:
A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together.

Tailored Spacer Structure Coating

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US Patent:
62361570, May 22, 2001
Filed:
Feb 26, 1999
Appl. No.:
9/258502
Inventors:
Lawrence S. Pan - Los Gatos CA
Donald R. Schropp - San Jose CA
Assignee:
Candescent Technologies Corporation - San Jose CA
International Classification:
H01J 162
H01J 6304
H01J 188
H01J 1942
H01J 178
US Classification:
313495
Abstract:
In a field emission display device, a spacer assembly and a method for forming a spacer assembly. In one embodiment, the present invention is comprised of a spacer wall which has a specific secondary electron emission coefficient function associated therewith. In the present embodiment, a coating material is then applied to at least a portion of the spacer wall. In this embodiment, the coating material has a secondary electron emission coefficient function which is different than the secondary electron emission coefficient function of the spacer wall. In so doing, the present embodiment provides a spacer assembly having a plurality of secondary electron emission coefficient functions associated therewith.

Voltage Ratio Regulator Circuit For A Spacer Electrode Of A Flat Panel Display Screen

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US Patent:
61539864, Nov 28, 2000
Filed:
Dec 23, 1999
Appl. No.:
9/470674
Inventors:
James C. Dunphy - San Jose CA
Donald R. Schropp - San Jose CA
Assignee:
Candescent Technologies Corporation - San Jose CA
International Classification:
G05F 100
US Classification:
315291
Abstract:
A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together.

Modulation Of Step Function Phenomena By Varying Nanoparticle Size

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US Patent:
20070238209, Oct 11, 2007
Filed:
Apr 4, 2007
Appl. No.:
11/696617
Inventors:
Zvi Yaniv - Austin TX, US
Donald R. Schropp - Austin TX, US
Assignee:
NANO-PROPRIETARY, INC. - Austin TX
International Classification:
H01L 21/00
US Classification:
438 36
Abstract:
The present invention is directed to methods and systems of modulating step function phenomena by varying nanoparticle size—particularly wherein a plurality of such nanoparticles are employed, and wherein said nanoparticles comprise a size distribution favorable for collectively smoothing the step function. Such methods and systems are particularly favorable for hydrogen sensors.
Donald Schropp from Sunnyvale, CA, age ~62 Get Report