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Douglas E Thorpe

from Albuquerque, NM
Age ~67

Douglas Thorpe Phones & Addresses

  • 13709 Poinsettia Ct SE, Albuquerque, NM 87123 (505) 294-7055
  • 13912 Encantado Rd NE, Albuquerque, NM 87123
  • Cloudcroft, NM
  • 13912 Encantado Rd NE, Albuquerque, NM 87123 (505) 294-7055

Work

Position: Professional Specialty Occupations

Education

Degree: Associate degree or higher

Specialities

Business and Entertainment Litigation • Contract • Real Estate • Commercial • Intellectual Property • Professional Liability • Fraud

Professional Records

Lawyers & Attorneys

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Douglas Thorpe - Lawyer

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Office:
Douglas Thorpe, APC
Specialties:
Business and Entertainment Litigation
Contract
Real Estate
Commercial
Intellectual Property
Professional Liability
Fraud
ISLN:
903152950
Admitted:
1969
University:
University of Nebraska, B.S.C.E., 1959
Law School:
Southern Methodist University, J.D., 1968

Resumes

Resumes

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Douglas Thorpe

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Location:
El Segundo, CA
Industry:
Design
Work:
Xilinx 2002 - 2011
Senior Staff Engineer

Honeywell Dec 1985 - Nov 2000
Staff Engineer

E-Systems Melpar Division Jan 1982 - Aug 1985
Design Engineer
Education:
Colorado State University 1979 - 1981
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Semiconductors
Design
Xilinx
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Douglas Thorpe

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Publications

Isbn (Books And Publications)

A New Earth: The Labor of Language in Pearl, Herbert's Temple, and Blake's Jerusalem

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Author

Douglas A. Thorpe

ISBN #

0813207282

Us Patents

Optimized Database Management System

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US Patent:
6430548, Aug 6, 2002
Filed:
Jan 18, 1994
Appl. No.:
08/182886
Inventors:
David L. Deis - Corrales NM
Robert M. Gjullin - Corrales NM
Douglas E. Thorpe - Albuquerque NM
Assignee:
Honeywell Inc. - Morristown NJ
International Classification:
G06F 1730
US Classification:
707 2, 707100
Abstract:
A computerized method for organizing data from multiple databases into a single database for optimal access. The method includes providing multiple databases, each for storing data in the form of records. A record from each database is read, and the several records are stored in a single record within a combined database. The single record has a format such the several records are each stored in accessible portions of the single record so that they can be retrieved individually or together.

Method And System For Inserting Probe Points In Fpga-Based System-On-Chip (Soc)

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US Patent:
6760898, Jul 6, 2004
Filed:
Feb 22, 2002
Appl. No.:
10/082517
Inventors:
Reno L. Sanchez - Albuquerque NM
Douglas E. Thorpe - Albuquerque NM
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 16, 716 4, 716 1, 716 17
Abstract:
Probe points can be inserted ( ) into an FPGA-based embedded processor SoC ( ) while specifying hardware and software cores with a design automation tool. This tool then aids the user (via high level GUI) in imbedding logic analysis functions in the SoC and connecting selected monitor signals to the logic analyzer. The design automation tool provides the necessary support files for the logic analysis software suite for naming and formatting of monitor signals on the waveform display. Trigger and trace information can be captured for the probe points and waveforms representing the captured information can be displayed ( ) for analysis. An integrated logic analyzer core can be downloaded ( ) into the FPGA-based embedded processor SoC to facilitate insertion of the probe points and capture of information. A software application can receive the captured information and translate it into a format suitable for display.

Circuit For And Method Of Realigning Data

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US Patent:
7398334, Jul 8, 2008
Filed:
Mar 12, 2004
Appl. No.:
10/800367
Inventors:
Douglas E. Thorpe - Albuquerque NM, US
Farrell L. Ostler - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 3/00
G06F 13/12
US Classification:
710 29, 710 30, 710 33, 710 51, 710 65
Abstract:
A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Circuit For And Method Of Realigning Data

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US Patent:
7827327, Nov 2, 2010
Filed:
Jun 11, 2008
Appl. No.:
12/137498
Inventors:
Douglas E. Thorpe - Albuquerque NM, US
Farrell L. Ostler - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 3/00
G06F 13/00
G06F 13/12
US Classification:
710 36, 710 31, 710 38, 710 65
Abstract:
A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Three Dimensional Computer Graphic Symbol Generator

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US Patent:
52261093, Jul 6, 1993
Filed:
Apr 26, 1990
Appl. No.:
7/514742
Inventors:
John F. Dawson - Albuquerque NM
Douglas E. Thorpe - Albuquerque NM
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G06F 1572
US Classification:
395120
Abstract:
An apparatus for generating three dimensional graphic symbols. Each symbol includes a plurality of polygons referenced to a datum point in a cartesian coordinate system, for example, having X, Y and Z axes. Apparatus for storing a vertex list is included. The vertex list characterizes each symbol and includes a starting address and a plurality of vertices, wherein each vertex is comprised of X, Y, and Z offsets from the datum point. In one embodiment, each vertex has a surface normal assigned to it. Connected to the vertex storing apparatus is an apparatus for registering an icon ID reference numeral to each symbol. An apparatus for mapping to the starting address is further connected to an output of the registering apparatus. The mapping apparatus uses the icon ID reference numeral to point to each symbol's starting address. Apparatus for transforming the vertex list into a different coordinate system is arranged to receive the vertex list from the vertex storing apparatus.

Method Of Sampling A Terrain Data Base

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US Patent:
56300352, May 13, 1997
Filed:
Jan 18, 1994
Appl. No.:
8/183533
Inventors:
Robert M. Gjullin - Corrales NM
Douglas E. Thorpe - Albuquerque NM
Assignee:
Honneywell Inc. - Minneapolis MN
International Classification:
G06F 1500
G05D 100
US Classification:
395127
Abstract:
A convergence model is shown and described for accommodating variation in data post spacing in a digital terrain elevation database (DTED) based on longitude and latitude address values for data posts. Under such a database structure, data posts lying along lines of latitude vary in spacing according to latitude, and converge at the poles with zero spacing therebetween. To scan a circular region of data posts relative to a given data post, e. g. , a threat installation, this variation in data post spacing is considered by appropriately scaling sample step spacing along radials traversed in executing a radial spoke scan pattern. In this manner, a circular region of data posts surrounding a given data post may be sampled using simple, dedicated hardware despite this variation in data post spacing.

Device Executing Intervisibility Calculation

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US Patent:
55262600, Jun 11, 1996
Filed:
Jun 8, 1995
Appl. No.:
8/488808
Inventors:
Thomas A. Kodet - Albuquerque NM
Marie A. Stoffer - Rio Rancho NM
Douglas E. Thorpe - Albuquerque NM
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G05D 100
US Classification:
364423
Abstract:
A device executing intervisibility calculation includes a mechanism executing a radial spoke scan pattern where individual radials are traversed beginning at a threat installation and extending outward along a radial to a distance corresponding to threat range capability. Intervisibility calculation is simplified to allow implementation in a simple, dedicated hardware engine to provide rapid execution time while ensuring accurate intervisibility results. The intervisibility engine includes lookup tables to provide precalculated data and advantageously avoids divide operations whereby the intervisibility calculation may be executed by use of a series of adds, subtracts, and multiplies relative to intervisibility data developed while traversing a given radial. The engine calculates a slope for each data post visited in traversing a radial, and identifies a data post as being visible when its associated slope is greater than a previously encountered greatest magnitude slope. The engine stores in a digital terrain elevation database an intervisibility ground reference value representing a magnitude of vertical clearance between a given data post elevation and a threat detection envelope thereabove.

Polygon Tiling Engine

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US Patent:
53718402, Dec 6, 1994
Filed:
Apr 21, 1994
Appl. No.:
8/231347
Inventors:
Douglas A. Fischer - Albuquerque NM
Douglas E. Thorpe - Albuquerque NM
Keith L. Jackson - Albuquerque NM
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G06F 1562
US Classification:
395133
Abstract:
A polygon tiling engine for use in a computer graphics display system. The computer graphics display system includes a high speed processor which provides lines of vertices, object type codes and START and STOP points for the vertex lines. The system further includes a VME bus. An improved apparatus for polygon tiling comprises apparatus for receiving the START and STOP points, instruction register apparatus coupled to the high speed processor for receiving instruction codes, object storing apparatus, a state machine for controlling the polygon tiling apparatus, a polygon address generating machine, a user defined object memory, a multiplexer and a triple buffered memory. Information is sent from the high speed processor to the tripled buffered memory, instruction registers and START and STOP registers. The information is processed into polygon addresses by the polygon generating apparatus. The polygon tiling apparatus is capable of tiling terrain data, multivertex polygons and user defined objects.
Douglas E Thorpe from Albuquerque, NM, age ~67 Get Report