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Eudes P Lopes

from San Diego, CA
Age ~64
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Also known as:
Eudes Prado Lopes, Eudes Lopes, Maria Lopes, Filho Eudes Lopes, Eudes Filho, Eudes Lopes Filho, O Lopes, Prado Lopes Eudes
Related to:
Patricia Lopes, 32Patricia Lopez, 36Erika Vanessa Lopez, 41Salvador E Lopez, 68Maria F Godinez, 39Lopes Eudes, 31Maria Prado Lopes, 61
Connected to:
Alicia Lopes, 57Alissa A Lopes, 39April Lopes, 37Bernardo C Lopes, 47Betty Lopes, 66Carlota T Lopes, 57Clecio G Lopes, 82Denny LopesEder C Lopes, 40Edimilson Lopes, 37

Eudes Lopes Phones & Addresses

  • San Diego, CA
  • 6328 Cloverhill Dr, San Jose, CA 95120
  • Irvine, CA
  • Ithaca, NY
  • Gilroy, CA

Work

Company: Cpqd Aug 2016 Position: Business development manager

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Sorbonne Université 1992 to 1996 Specialities: Computer Science

Skills

Soc • Asic • Integrated Circuit Design • Ic • Semiconductors • Physical Design • Microelectronics • Eda • Cmos • Vlsi • Physical Verification • Mixed Signal • Rtl Design • Fpga • Static Timing Analysis • Cadence • Digital Design • Analog Circuit Design • Functional Verification • Verilog • Hardware Architecture • Systemverilog • Analog • Circuit Design • Cadence Virtuoso • Tcl • Vhdl • Rtl Coding • Xilinx • Simulations • Dft • Primetime • Layout • Teaching • Digital Signal Processors • Low Power Design • Microprocessors • Lvs • Modelsim • Logic Synthesis • Formal Verification • Chip Design Services Business • Very Large Scale Integration • System on A Chip • Application Specific Integrated Circuits • Integrated Circuits • Field Programmable Gate Arrays

Languages

English • French • Portuguese • Spanish

Industries

Information Technology And Services

Resumes

Resumes

Eudes Lopes Photo 1

Business Development Manager

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Location:
San Diego, CA
Industry:
Information Technology And Services
Work:
Cpqd
Business Development Manager
Cpqd
Manager, Microelectronics Design Services Center - Gto and Drc
Cpqd Jan 2013 - Dec 2013
Pesquisador Especialista Ii
Imec Nov 2008 - Oct 2012
Soc Design Engineer
Nxp Semiconductors Aug 1999 - Sep 2008
Senior Design Engineer
Education:
Sorbonne Université 1992 - 1996
Doctorates, Doctor of Philosophy, Computer Science Universidade Federal Do Rio De Janeiro 1987 - 1989
Colégio Brasil América
Universidade Federal Do Rio De Janeiro
Université Pierre - Et - Marie - Curie
Doctorates, Doctor of Philosophy, Computer Science, Electronics Universidade Federal Do Rio De Janeiro
Master of Science, Masters, Electronics Engineering
Skills:
Soc
Asic
Integrated Circuit Design
Ic
Semiconductors
Physical Design
Microelectronics
Eda
Cmos
Vlsi
Physical Verification
Mixed Signal
Rtl Design
Fpga
Static Timing Analysis
Cadence
Digital Design
Analog Circuit Design
Functional Verification
Verilog
Hardware Architecture
Systemverilog
Analog
Circuit Design
Cadence Virtuoso
Tcl
Vhdl
Rtl Coding
Xilinx
Simulations
Dft
Primetime
Layout
Teaching
Digital Signal Processors
Low Power Design
Microprocessors
Lvs
Modelsim
Logic Synthesis
Formal Verification
Chip Design Services Business
Very Large Scale Integration
System on A Chip
Application Specific Integrated Circuits
Integrated Circuits
Field Programmable Gate Arrays
Languages:
English
French
Portuguese
Spanish
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Eudes P Lopes from San Diego, CA, age ~64 Get Report