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Eugene J Ye

from San Francisco, CA
Age ~28
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Related to:
Yanping Ping Chen, 81Maggie B Li, 37Huiting Tan, 50Hui C YeJeanie Ye, 31Jin Y Ma, 60Li Y Ye, 58Jun Ye, 41Jie Yuan, 30Lukang Yu, 61Robert Yu, 60Yong C Tan, 39Gui Y Chen, 58
Connected to:
Bihui Ye, 58Jason Z Ye, 50Jiawen Ye, 40Lian Ye, 39Lucy Ye, 31Madeline Ye, 30Minyi Ye, 34Queenie YeRick W Ye, 63Ritchie B Ye, 42

Eugene Ye Phones & Addresses

  • San Francisco, CA
  • San Jose, CA

Resumes

Resumes

Eugene Ye Photo 1

Senior Director, Physical Design Group

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Location:
Berkeley, CA
Industry:
Semiconductors
Work:
Marvell Semiconductor
Senior Director, Physical Design Group
Education:
University of Michigan
Skills:
Semiconductors
Physical Design
Eugene Ye Photo 2

Eugene Ye

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Location:
San Francisco, CA
Work:
San Jose State University
Education:
San Jose State University 2013 - 2018
Eugene Ye Photo 3

Assistant Property Manager

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Location:
San Francisco, CA
Industry:
Financial Services
Work:
Colliers International
Assistant Property Manager
Shorenstein Realty Services Jul 2016 - Dec 2017
Tenant Services Administrator
Assist Marketing Feb 2012 - Jun 2016
Brand Ambassador
Education:
San Francisco State University 2014 - 2016
Bachelors, Finance
Skills:
Marketing
Brand Awareness
Communication
Customer Service
Social Media
Sales
Powerpoint
Microsoft Office
Microsoft Word
Social Media Marketing
Commercial Real Estate
Eugene Ye Photo 4

Eugene Ye

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Eugene Ye Photo 5

Eugene Ye

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Publications

Us Patents

Circuitry Having Programmable Power Rails, Architectures, Apparatuses, And Systems Including The Same, And Methods And Algorithms For Programming And/Or Configuring Power Rails In An Integrated Circuit

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US Patent:
8635572, Jan 21, 2014
Filed:
Apr 9, 2013
Appl. No.:
13/859220
Inventors:
- Hamilton, BM
Eugene Ye - Saratoga CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 17/50
US Classification:
716120, 716118, 716119, 716126, 716127, 716128, 716129, 716130, 716132, 716133, 716135, 716139, 326 30, 326 33, 326 41, 326 47, 326 63, 326 80
Abstract:
Circuits, architectures, a system and methods for providing multiple power rails to a plurality of standard cells in a region of an integrated circuit. The circuitry generally includes a plurality of cells configured for connection to a first or second power rail, the first power rail providing a first voltage to at least one of the plurality of cells, and the second power rail providing a second voltage (which may be independent from the first voltage) to remaining cells in the plurality of cells. The method generally includes routing, in an IC layout, a first power rail providing a first voltage and a second power rail providing a second voltage, placing the plurality of cells, and selectively connecting first and second subsets of the plurality of cells to the first and second power rails, respectively. The present invention further advantageously minimizes regional layout design considerations and time delays.

Circuitry Having Programmable Power Rails, Architectures, Apparatuses, And Systems Including The Same, And Methods And Algorithms For Programming And/Or Configuring Power Rails In An Integrated Circuit

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US Patent:
8423946, Apr 16, 2013
Filed:
May 19, 2011
Appl. No.:
13/111435
Inventors:
Jianwen Jin - Los Altos CA, US
Eugene Ye - Saratoga CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 17/50
US Classification:
716133, 716126, 716127, 716128, 716132
Abstract:
Circuits, architectures, a system and methods for providing multiple power rails to a plurality of standard cells in a region of an integrated circuit. The circuitry generally includes a plurality of cells configured for connection to a first or second power rail, the first power rail providing a first voltage to at least one of the plurality of cells, and the second power rail providing a second voltage (which may be independent from the first voltage) to remaining cells in the plurality of cells. The method generally includes routing, in an IC layout, a first power rail providing a first voltage and a second power rail providing a second voltage, placing the plurality of cells, and selectively connecting first and second subsets of the plurality of cells to the first and second power rails, respectively. The present invention further advantageously minimizes regional layout design considerations and time delays.
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Eugene J Ye from San Francisco, CA, age ~28 Get Report