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Gregory Ray Goslin

from Los Gatos, CA
Deceased
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Also known as:
Gregory R Goslin, Greg R Goslin, Gregory R Gold
Phone and address:
258 Edelen Ave, Los Gatos, CA 95030
(408) 354-4920
Related to:
Ronald GoslinCatherine Goslin, 54Erlinda GoldDavid G Volkert, 54Dennis I Goslin, 86Dennis I GoslinCharlene Goslin, 74Marvin B Gold, 91Brennen T GoslinAlexander N GoslinDiana L Goslin, 60
Connected to:
Gary Goslin, 57Meghan Goslin, 39Brian C Gosling, 57Curtis L Gosling, 61Melinda Gosling, 36Philip H Gosling, 83Thomas J Gosline, 59Gretchen P Gosma, 47Robert D Gosma, 59Brian M Gosnell, 65

Gregory Goslin Phones & Addresses

  • 258 Edelen Ave, Los Gatos, CA 95030 (408) 354-4920 (408) 395-0472
  • San Jose, CA
  • Chico, CA
  • Idaho Falls, ID
  • Sunnyvale, CA
  • Seattle, WA
  • Santa Clara, CA

Work

Company: Texas instruments Aug 2003 Position: Lead architect, vlsi design

Industries

Telecommunications

Resumes

Resumes

Gregory Goslin Photo 1

Lead Architect, Vlsi Design

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Location:
Los Gatos, CA
Industry:
Telecommunications
Work:
Texas Instruments
Lead Architect, Vlsi Design
Droplet Technology Sep 2002 - Aug 2003
Director Engineering, Vlsi and Fpga Group
Morphics Technology Dec 1998 - Jul 2002
Manager Drl Engineering, Vlsi and Fpga Group
Diablo Research Company Jan 1996 - Dec 1998
Senior Project Engineer, Wireless Group
Xilinx Oct 1993 - May 1996
Dsp Applications Manager, Dsp Product Development Team

Publications

Us Patents

Flexible Preamble Processing For Detecting A Code Sequence

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US Patent:
6694496, Feb 17, 2004
Filed:
Aug 3, 2001
Appl. No.:
09/922406
Inventors:
Gregory R. Goslin - Los Gatos CA
Venugopal Balasubramonian - Campbell CA
Assignee:
Morphics Technology, Inc. - Cambell CA
International Classification:
G06F 1750
US Classification:
716 4, 716 1
Abstract:
An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.

System And Method For Enhanced Symbol Generation

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US Patent:
7627064, Dec 1, 2009
Filed:
Jun 30, 2006
Appl. No.:
11/479570
Inventors:
Ahmed Said - Saratoga CA, US
Elias Nemer - San Jose CA, US
Gregory R. Goslin - Los Gatos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04B 1/10
US Classification:
375350
Abstract:
According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Effective Adaptive Filtering Techniques

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US Patent:
7826523, Nov 2, 2010
Filed:
Mar 31, 2006
Appl. No.:
11/395412
Inventors:
Ahmed Said - Saratoga CA, US
Elias J. Nemer - San Jose CA, US
Gregory R. Goslin - Los Gatos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03H 7/30
H04L 27/06
H04B 1/10
US Classification:
375232, 375233, 375340, 455295
Abstract:
A noise level of an input signal is determined by a noise calculation module. based on the noise level, a boundary setting module sets a reduced constellation boundary interval. This reduced constellation boundary interval is employed by an equalizer to perform adaptive equalization of the input signal.

System And Method For Enhanced Symbol Generation

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US Patent:
8059762, Nov 15, 2011
Filed:
Oct 21, 2009
Appl. No.:
12/603192
Inventors:
Ahmed Said - Saratoga CA, US
Elias Nemer - San Jose CA, US
Gregory R. Goslin - Los Gatos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 27/06
US Classification:
375340
Abstract:
According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Fluid Sensor And Methods Of Making Components Thereof

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US Patent:
20090120169, May 14, 2009
Filed:
Nov 12, 2007
Appl. No.:
11/938621
Inventors:
Douglas B. McNeil - Monte Sereno CA, US
Gregory Ray Goslin - Los Gatos CA, US
International Classification:
G01N 11/16
H01L 41/22
US Classification:
73 5441, 29 2535
Abstract:
A fluid sensor has an electrically grounded header and a plurality of feedthrough conductors extending through the header between opposite ends of the header. The feedthrough conductors are connected to a piezoelectric tuning fork resonator. A temperature sensor is adjacent the tuning fork resonator. A shroud partially encloses the tuning fork resonator and temperature sensor. A printed circuit board is in conductive electrical contact with the feedthrough conductors. The printed circuit board includes an ASIC chip operable to transmit a variable frequency signal to the tuning fork resonator through the feedthrough conductors to oscillate the tuning fork resonator and to monitor impedance of the tuning fork resonator as a function of frequency. The ASIC chip is spaced from the feedthrough conductors a distance of no more than about 2 mm. The printed circuit board is spaced from the tuning fork a distance of no more than about 20 mm.

Method And Apparatus For Generating Optimized Functional Macros

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US Patent:
61205494, Sep 19, 2000
Filed:
Jan 6, 1997
Appl. No.:
8/777272
Inventors:
Gregory R. Goslin - Los Gatos CA
Bart C. Thielges - San Jose CA
Steven H. Kelem - Los Altos Hills CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
703 20
Abstract:
A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within different parameter ranges.
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Gregory Ray Goslin from Los Gatos, CADeceased Get Report