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Hui Yin Seto

from San Jose, CA
Age ~60
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Also known as:
Hui Y Seto, Huiyin Seto, Hui I
Phone and address:
3067 Flater Dr, San Jose, CA 95148
(408) 270-1568
Related to:
Sangdok D KimEun Shin, 44Min Shin, 45Kyung P Shin, 71Hwang ShimRobert Chen, 52
Connected to:
Johnny K Seto, 63Kazuto Seto, 101Maria N Seto, 58Mary K Seto, 73Mason Y Seto, 55Patty SetoStephen L Seto, 39Vivian H Seto, 34Josiah SetonKeith A Setree, 63

Hui Seto Phones & Addresses

  • 3067 Flater Dr, San Jose, CA 95148 (408) 270-1568
  • Chico, CA
  • Santa Clara, CA
  • 3067 Flater Dr, San Jose, CA 95148 (408) 239-3258

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

n***[email protected]

Publications

Us Patents

Macro Cell For Integrated Circuit Physical Layer Interface

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US Patent:
20050229132, Oct 13, 2005
Filed:
Mar 26, 2004
Appl. No.:
10/810294
Inventors:
Derrick Butt - San Leandro CA, US
Bruce Cochrane - San Jose CA, US
Hui Seto - San Jose CA, US
William Lau - Foster City CA, US
Thomas McCarthy - Cary NC, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
US Classification:
716010000
Abstract:
A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.

Low-Power, Programmable Multi-Stage Delay Cell

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US Patent:
20080068060, Mar 20, 2008
Filed:
Sep 14, 2006
Appl. No.:
11/531829
Inventors:
Keven Hui - San Ramon CA, US
Ting Fang - Pleasanton CA, US
Hui Yin Seto - San Jose CA, US
International Classification:
H03H 11/26
US Classification:
327261
Abstract:
A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.
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Hui Yin Seto from San Jose, CA, age ~60 Get Report