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Kimihiko I Imura

from Encinitas, CA
Age ~67

Kimihiko Imura Phones & Addresses

  • 716 Cypress Hills Dr, Encinitas, CA 92024 (858) 794-1849
  • La Jolla, CA
  • 12922 Caminito Beso, San Diego, CA 92130
  • 13687 Essence Rd, San Diego, CA 92128
  • 2575 Jerome St, Pocatello, ID 83201

Publications

Us Patents

Method And System For Improved Analog Performance In Sub-100 Nanometer Cmos Transistors

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US Patent:
20140001553, Jan 2, 2014
Filed:
Jun 25, 2013
Appl. No.:
13/926603
Inventors:
Kimihiko Imura - San Diego CA, US
International Classification:
H01L 27/092
H01L 21/8238
US Classification:
257344, 438217
Abstract:
Methods and systems for improved analog performance of core CMOS transistors may comprise a semiconductor die comprising both input/output (I/O) complementary metal oxide semiconductor (CMOS) transistors and core CMOS transistors. A doping profile of a subset of the core CMOS transistors may comprise lightly-doped drain and pocket implant layers between source and drain layers below a gate insulator, and a doping profile of another subset of the core CMOS transistors may be constant between source and drain layer. The core CMOS devices may comprise sub-100 nanometer gate lengths. An output resistance of the second subset of the core CMOS transistors may be increased by the constant doping profile between the source and drain layers. The second subset of the core CMOS transistors may be operable to amplify analog signals. The first subset of the core CMOS transistors may be operable to process digital signals.

Method And System For Improved Matching For On-Chip Capacitors

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US Patent:
20130334658, Dec 19, 2013
Filed:
Jun 13, 2013
Appl. No.:
13/917147
Inventors:
Weizhong Cai - Vista CA, US
Kimihiko Imura - San Diego CA, US
Wei Gu - Vista CA, US
International Classification:
H01L 49/02
US Classification:
257532, 438381
Abstract:
Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

Method And System For Improved Matching For On-Chip Capacitors

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US Patent:
20180323135, Nov 8, 2018
Filed:
Jul 9, 2018
Appl. No.:
16/030397
Inventors:
- Carlsbad CA, US
Kimihiko Imura - Carlsbad CA, US
Wei Gu - Carlsbad CA, US
International Classification:
H01L 23/495
H01L 23/522
H01L 49/02
H01L 21/48
H01L 27/02
Abstract:
Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

Method And System For Improved Matching For On-Chip Capacitors

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US Patent:
20170148712, May 25, 2017
Filed:
Nov 24, 2015
Appl. No.:
14/950865
Inventors:
- Carlsbad CA, US
Kimihiko Imura - Carlsbad CA, US
Wei Gu - Carlsbad CA, US
International Classification:
H01L 23/495
H01L 21/48
Abstract:
Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.
Kimihiko I Imura from Encinitas, CA, age ~67 Get Report