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Martin L Culley

from Boise, ID
Age ~66
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Also known as:
Lamar Culley Martin
Phone and address:
6002 E Grand Prairie Dr, Boise, ID 83716
(801) 645-9021
Related to:
Darrell L Dudley, 74Tristan Martin, 29Debra J Martin, 69Katie T Martin, 40Travis R Martin, 47Nathan D Martin, 42Riley R Martin, 70
Connected to:
Bryan M Culley, 43Channin G Culley, 54Danielle Culley, 49Marianne E Culley, 73Rockey Culley, 50Ryan L Culley, 51Darryl W Cullick, 54Robert L Cullifer, 63Taylor Cullifer, 32David P Culligan, 57

Martin Culley Phones & Addresses

  • 6002 E Grand Prairie Dr, Boise, ID 83716 (801) 645-9021
  • 5517 175 E, Ogden, UT 84405
  • Layton, UT
  • Roy, UT
  • Berthoud, CO
  • Tucson, AZ

Work

Company: Micron technology Sep 1, 2008 Position: Memory systems design engineer

Education

School / High School: Utah State University Specialities: Electrical Engineering

Skills

Arm • Firmware • Embedded Systems • Asic • Hardware Architecture • Sata • Scsi • Fpga • Soc • Device Drivers • Verilog • Usb • Ssd • Flash Memory • Debugging • Hardware • Storage

Industries

Computer Hardware

Resumes

Resumes

Martin Culley Photo 1

Memory Systems Design Engineer

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Location:
Boise, ID
Industry:
Computer Hardware
Work:
Micron Technology
Memory Systems Design Engineer
Iomega Feb 1996 - Jul 2008
Principal Engineer
Maxtor Aug 1991 - Feb 1996
Senior Staff Engineer
Areal Technology Jun 1988 - Aug 1991
Engineering Manager
Education:
Utah State University
Utah State University
Bachelors, Bachelor of Science, Computer Science
Skills:
Arm
Firmware
Embedded Systems
Asic
Hardware Architecture
Sata
Scsi
Fpga
Soc
Device Drivers
Verilog
Usb
Ssd
Flash Memory
Debugging
Hardware
Storage

Publications

Us Patents

Method And Circuitry For Switching From A Synchronous Mode Of Operation To An Asynchronous Mode Of Operation Without Any Loss Of Data

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US Patent:
6715095, Mar 30, 2004
Filed:
Oct 2, 2000
Appl. No.:
09/677390
Inventors:
Troy Larsen - North Ogden UT
Martin Culley - Ogden UT
Assignee:
Iomeca Corporation - San Diego CA
International Classification:
G06F 132
US Classification:
713600, 713324, 713601
Abstract:
An integrated circuit chip that receives data on an asynchronous communications bus from an external device and receives data from asynchronous internal device is capable of switching from synchronous operation to asynchronous operation without any loss of data. The chip does not switch off the system clock while there is activity on the communications bus. Additionally, the communications bus has a minimum event time greater than the time fo one and a half cycles of the system clock plus enough timing margin for an asynchronous update to occur.

Method And Apparatus For Detecting And Correcting Errors In Stored Information

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US Patent:
7587656, Sep 8, 2009
Filed:
May 29, 2003
Appl. No.:
10/447923
Inventors:
Troy D. Larsen - North Ogden UT, US
Martin L. Culley - Ogden UT, US
Marvin R. DeForest - Niwot CO, US
Assignee:
Iomega Corporation - San Diego CA
International Classification:
H03M 13/00
US Classification:
714769
Abstract:
A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.

Disk Controller Architecture To Allow On-The-Fly Error Correction And Write Disruption Detection

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US Patent:
7761770, Jul 20, 2010
Filed:
Jun 29, 2006
Appl. No.:
11/478244
Inventors:
Troy D. Larsen - North Ogden UT, US
Adam T. Arnell - Syracuse UT, US
Martin L. Culley - Ogden UT, US
Don W. Wallentine - Mantua UT, US
Facil T. Feye - West Jordan UT, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
H03M 13/00
US Classification:
714758, 714763, 714769
Abstract:
Error correction in a disk drive is performed by error correction circuitry which accepts data read from a data storage medium. The error correction circuitry performs both block error correction in a first data domain and sector error correction in a second data domain. A sector FIFO buffer is used to facilitate the error correction in real time, or “on-the-fly. ” The sector FIFO buffer also enables conversion of the corrected data to the first data domain. The error correction circuitry also generates an ECC block comprising a plurality of sectors and writes the ECC block. The circuitry generates a tag prior to writing the ECC block and adds the tag to each of a plurality of sectors. During a read operation, the circuitry detects a write disruption when the tags for all of the plurality of sectors in the ECC block are not identical.

Data Recovery In A Solid State Storage System

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US Patent:
8327224, Dec 4, 2012
Filed:
Apr 16, 2009
Appl. No.:
12/424766
Inventors:
Troy Larsen - North Ogden UT, US
Martin Culley - Boise ID, US
Troy Manning - Meridian ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03M 13/00
US Classification:
714763
Abstract:
Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.

Memory Address Translation

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US Patent:
8417914, Apr 9, 2013
Filed:
Jan 6, 2011
Appl. No.:
12/985787
Inventors:
Troy A. Manning - Meridian ID, US
Martin L. Culley - Boise ID, US
Troy D. Larsen - Meridian ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 12/00
US Classification:
711202, 711 3, 711103, 711118, 711170, 711221
Abstract:
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Logical Address Translation

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US Patent:
20120226887, Sep 6, 2012
Filed:
Mar 6, 2011
Appl. No.:
13/041402
Inventors:
Martin L. Culley - Boise ID, US
Troy A. Manning - Meridian ID, US
Troy D. Larsen - Meridian ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
G06F 12/10
G06F 12/14
US Classification:
711202, 713193, 711E12058
Abstract:
The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Data Protection Across Multiple Memory Blocks

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US Patent:
20120311406, Dec 6, 2012
Filed:
May 31, 2011
Appl. No.:
13/118638
Inventors:
Sampath K. Ratnam - Boise ID, US
Troy D. Larsen - Meridian ID, US
Doyle W. Rivers - Rancho Cordova CA, US
Troy A. Manning - Meridian ID, US
Martin L. Culley - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
G06F 11/10
US Classification:
714768, 714E11034
Abstract:
Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.

Data Recovery In A Solid State Storage System

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US Patent:
20130080860, Mar 28, 2013
Filed:
Nov 16, 2012
Appl. No.:
13/678934
Inventors:
MICRON TECHNOLOGY, INC - Boise ID, US
Martin Culley - Boise ID, US
Troy Manning - Meridian ID, US
Assignee:
MICRON TECHNOLOGY, INC - Boise ID
International Classification:
H03M 13/05
US Classification:
714773, 714E11091
Abstract:
Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
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Martin L Culley from Boise, ID, age ~66 Get Report