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Mohammed T Quddus

from Chandler, AZ
Age ~57
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Also known as:
Mohammed Tanvir Quddus, Mohammed Quddus, Tanvir Dr Quddus, Mohamed Quddus, Mohammed S, Mdtanvir Quddus, Tanvir Quddus
Related to:
Farhana Hussain, 51Hussain Faheem, 43
Connected to:
Syed QudratullahBobby J Que, 68Lisa Que, 60Sera QueAndrea D Queale, 53William L Quealy, 72Jeannine A Quear, 47Joshua M QuebadaRobert C Quebbeman, 75Jon C Quebe, 53

Mohammed Quddus Phones & Addresses

  • Chandler, AZ
  • Maricopa, AZ
  • 1255 University Dr, Tempe, AZ 85281 (480) 894-6824

Professional Records

Medicine Doctors

Mohammed Quddus Photo 1

Mohammed Ruhul Quddus

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Specialties:
Pathology
Anatomic Pathology & Clinical Pathology
Education:
Dhaka Medical College (1983)

Publications

Us Patents

Low Threshold Compact Mos Device With Channel Region Formed By Outdiffusion Of Two Regions And Method Of Making Same

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US Patent:
6507058, Jan 14, 2003
Filed:
Oct 17, 2000
Appl. No.:
09/690876
Inventors:
Jefferson W. Hall - Phoenix AZ
Mohamed Imam - Tempe AZ
Zia Hossain - Tempe AZ
Mohammed Tanvir Quddus - Tempe AZ
Joe Fulton - Chandler AZ
Assignee:
Semiconductor Components Industries LLC - Phoenix AZ
International Classification:
H01L 2980
US Classification:
257285, 257288, 257335, 257344, 257387, 257404, 438289, 438291
Abstract:
A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Nmosfet With Negative Voltage Capability Formed In P-Type Substrate And Method Of Making The Same

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US Patent:
6555877, Apr 29, 2003
Filed:
Aug 27, 2001
Appl. No.:
09/939552
Inventors:
Mohamed Imam - Tempe AZ
Raj Nair - Chandler AZ
Mohammed Tanvir Quddus - Tempe AZ
Masaru Suzuki - Aizuwakamatsu, JP
Takeshi Ishiguro - Aizuwakamatsu, JP
Jefferson W. Hall - Phoenix AZ
Assignee:
Semiconductor Components Industries LLC - Phoenix AZ
International Classification:
H01L 2701
US Classification:
257355, 257348, 257357
Abstract:
A semiconductor device ( ) is disclosed which can accommodate a negative voltage on its source using a P-type substrate ( ) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region ( ) is recessed by a dimension (X) from a first insulated region ( ). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure ( ) having a shape which surrounds a drain contact region ( ) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region ( ) is formed in a P-type region ( ) centered inside the gate structure ( ).

High Voltage Lateral Fet Structure With Improved On Resistance Performance

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US Patent:
7126166, Oct 24, 2006
Filed:
Mar 11, 2004
Appl. No.:
10/797537
Inventors:
Rajesh S. Nair - Chandler AZ, US
Shanghui Larry Tu - Phoenix AZ, US
Zia Hossain - Tempe AZ, US
Mohammed Tanvir Quddus - Chandler AZ, US
Assignee:
Semiconductor Components Industries, L.L.C. - Phoenix AZ
International Classification:
H01L 29/32
H01L 29/36
H01L 29/417
US Classification:
257110, 257107, 257120
Abstract:
In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Semiconductor Structure With Improved On Resistance And Breakdown Voltage Performance

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US Patent:
7276766, Oct 2, 2007
Filed:
Aug 1, 2005
Appl. No.:
11/193725
Inventors:
Shanghui Larry Tu - Phoenix AZ, US
James Adams - Tempe AZ, US
Mohammed Quddus - Chandler AZ, US
Rajesh S. Nair - Milpitas CA, US
Assignee:
Semiconductor Components Industries, L.L.C. - Phoenix AZ
International Classification:
H01L 29/76
H01L 29/94
H01L 31/00
US Classification:
257343
Abstract:
A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.

High Voltage Sensor Device And Method Therefor

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US Patent:
7306999, Dec 11, 2007
Filed:
Jan 25, 2005
Appl. No.:
11/041710
Inventors:
Jefferson W. Hall - Chandler AZ, US
Mohammed Tanvir Quddus - Chandler AZ, US
Assignee:
Semiconductor Components Industries, L.L.C. - Phoenix AZ
International Classification:
H01L 21/8222
US Classification:
438329, 438382, 257528, 257536, 257E21004
Abstract:
In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.

High Voltage Sensor Device

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US Patent:
7638405, Dec 29, 2009
Filed:
Oct 26, 2007
Appl. No.:
11/925017
Inventors:
Jefferson W. Hall - Chandler AZ, US
Mohammed Tanvir Quddus - Chandler AZ, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H01L 21/8222
US Classification:
438329, 438382, 257528, 257536, 257E21004
Abstract:
In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.

Method Of Forming A High Voltage Sense Element

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US Patent:
7803643, Sep 28, 2010
Filed:
Jan 22, 2010
Appl. No.:
12/692411
Inventors:
Jefferson W. Hall - Chandler AZ, US
Mohammed Tanvir Quddus - Chandler AZ, US
Assignee:
Semiconductor Component Industries, LLC - Phoenix AZ
International Classification:
H01L 21/66
US Classification:
438 17, 438 5, 438 10, 438382
Abstract:
In one embodiment, a method of forming a high voltage element includes forming a sense element overlying at least a portion of a semiconductor substrate, and also includes operably coupling a first circuit to use a sense signal formed by the sense element for one of detecting a line under-voltage condition, detecting a line over-voltage condition, determining input power, limiting input power, power limiting, controlling standby operation, a line feed-forward function for current mode ramp compensation, regulating an output voltage, or detecting an energy transfer state of an energy storage element.

High Voltage Sensor Device And Method Therefor

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US Patent:
7955943, Jun 7, 2011
Filed:
Sep 30, 2009
Appl. No.:
12/570300
Inventors:
Jefferson W. Hall - Chandler AZ, US
Mohammed Tanvir Quddus - Chandler AZ, US
Richard S. Burton - Phoenix AZ, US
Kazunori Oikawa - Sendai, JP
George Chang - Tempe AZ, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H01L 21/02
US Classification:
438382, 438 5, 438 10, 438 17, 257E21003, 257E21531
Abstract:
In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.
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Mohammed T Quddus from Chandler, AZ, age ~57 Get Report