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Paul R Bernatis

from Castro Valley, CA
Age ~62

Paul Bernatis Phones & Addresses

  • 3180 Carleen Dr, Castro Valley, CA 94546 (408) 393-2538
  • Hayward, CA
  • 107 Mary Ave, Sunnyvale, CA 94086
  • Salt Lake City, UT
  • Bend, OR

Publications

Us Patents

Systems And Methods For Harvesting And Reducing Contamination In Nanowires

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US Patent:
7741197, Jun 22, 2010
Filed:
Dec 20, 2006
Appl. No.:
11/643025
Inventors:
Xiangfeng Duan - Mountain View CA, US
Paul Bernatis - Sunnyvale CA, US
Alice Fischer-Colbrie - Redwood City CA, US
James M. Hamilton - Sunnyvale CA, US
Francesco Lemmi - Sunnyvale CA, US
Yaoling Pan - Union City CA, US
J. Wallace Parce - Palo Alto CA, US
David P. Stumbo - Belmont CA, US
Assignee:
Nanosys, Inc. - Palo Alto CA
International Classification:
H01L 21/20
H01L 21/36
US Classification:
438478, 438487, 977700, 977742
Abstract:
The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.

Electronic Grade Metal Nanostructures

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US Patent:
7976646, Jul 12, 2011
Filed:
Aug 18, 2006
Appl. No.:
11/506769
Inventors:
Srikanth Ranganathan - Mountain View CA, US
Paul Bernatis - Sunnyvale CA, US
Joel Gamoras - Vallejo CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US
Assignee:
Nanosys, Inc. - Palo Alto CA
International Classification:
C22C 5/04
B32B 15/02
US Classification:
148430, 420462, 428546
Abstract:
Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.

Nanocrystal Doped Matrixes

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US Patent:
8425803, Apr 23, 2013
Filed:
Nov 9, 2009
Appl. No.:
12/590619
Inventors:
J. Wallace Parce - Palo Alto CA, US
Paul Bernatis - Sunnyvale CA, US
Robert Dubrow - San Carlos CA, US
William P. Freeman - San Mateo CA, US
Joel Gamoras - Vallejo CA, US
Shihai Kan - San Jose CA, US
Andreas Meisel - Redwood City CA, US
Baixin Qian - Cupertino CA, US
Jeffery A. Whiteford - Belmont CA, US
Jonathan Ziebarth - Santa Barbara CA, US
Assignee:
Samsung Electronics Co., Ltd.
International Classification:
C30B 23/00
C30B 25/00
C30B 28/12
C30B 28/14
US Classification:
2523016S, 428403, 428404, 427212, 427215, 977813, 977824
Abstract:
Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.

Nanocrystal Doped Matrixes

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US Patent:
8592037, Nov 26, 2013
Filed:
Oct 20, 2011
Appl. No.:
13/277361
Inventors:
J. Wallace Parce - Palo Alto CA, US
Paul Bernatis - Sunnyvale CA, US
Robert Dubrow - San Carlos CA, US
William P Freeman - San Mateo CA, US
Joel Gamoras - Vallejo CA, US
Shihai Kan - San Jose CA, US
Andreas Meisel - Redwood City CA, US
Baixin Qian - Sunnyvale CA, US
Jeffery A Whiteford - Belmont CA, US
Jonathan Ziebarth - Palo Alto CA, US
Assignee:
Samsung Electronics Co., Ltd.
International Classification:
B32B 9/04
US Classification:
428405, 523212, 523213, 528 15, 528 26, 528 30, 556439, 556405
Abstract:
Compositions containing a nanostructure, preferably a nanocrystal, are provided. The nanostructures have ligands bound to the surface. Such ligands are preferably siloxane containing ligands having at least one —COON group, although ligands having various ═P═O groups are also contemplated. The nanostructures can be embedded into a polymer such as a silicone polymer.

Nanocrystal Doped Matrixes

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US Patent:
20070034833, Feb 15, 2007
Filed:
Jul 24, 2006
Appl. No.:
11/492717
Inventors:
J. Parce - Palo Alto CA, US
Paul Bernatis - Sunnyvale CA, US
Robert Dubrow - San Carlos CA, US
William Freeman - San Mateo CA, US
Joel Gamoras - Vallejo CA, US
Shihai Kan - San Jose CA, US
Andreas Meisel - Redwood City CA, US
Baixin Qian - Sunnyvale CA, US
Jeffery Whiteford - Belmont CA, US
Jonathan Ziebarth - Palo Alto CA, US
International Classification:
C09K 11/02
US Classification:
252301360, 428690000
Abstract:
Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.

Electronic Grade Metal Nanostructures

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US Patent:
20110251295, Oct 13, 2011
Filed:
May 27, 2011
Appl. No.:
13/118020
Inventors:
Srikanth Ranganathan - Mountain View CA, US
Paul Bernatis - Hayward CA, US
Joel Gamoras - Vallejo CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US
Assignee:
NANOSYS, INC. - Palo Alto CA
International Classification:
C09K 3/00
B82Y 30/00
US Classification:
516 97, 516 78, 25218233, 977774
Abstract:
Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.

Composition For Cleaning Substrates Post-Chemical Mechanical Polishing

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US Patent:
20130053291, Feb 28, 2013
Filed:
Aug 22, 2011
Appl. No.:
13/214920
Inventors:
Atsushi Otake - Kawasaki-shi, JP
Paul R. Bernatis - Hayward CA, US
Cass X. Shang - Sunnyvale CA, US
International Classification:
C11D 3/60
C11D 7/60
US Classification:
510175
Abstract:
A semiconductor processing composition and method for cleaning semiconductor wafers post chemical mechanical polishing comprising a phosphorous base and optionally at least one surfactant.
Paul R Bernatis from Castro Valley, CA, age ~62 Get Report