US Patent:
20210318909, Oct 14, 2021
Inventors:
- Cupertino CA, US
John G. Dorsey - San Francisco CA, US
James M. Magee - Orlando FL, US
Daniel A. Chimene - San Francisco CA, US
Cyril de la Cropte de Chanterac - San Francisco CA, US
Bryan R. Hinch - Mountain View CA, US
Aditya Venkataraman - Sunnyvale CA, US
Andrei Dorofeev - San Jose CA, US
Nigel R. Gamble - San Francisco CA, US
Russell A. Blaine - San Carlos CA, US
Constantin Pistol - Cupertino CA, US
James S. Ismail - Sunnyvale CA, US
International Classification:
G06F 9/50
G06F 9/48
G06F 1/3234
G06F 1/329
G06F 1/3296
G06F 9/38
G06F 9/26
G06F 9/54
G06F 1/20
G06F 1/324
Abstract:
Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.