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Albert F Fazio

from Saratoga, CA
Age ~63
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Also known as:
Al Fazio
Phone and address:
19900 Douglass Ln, Saratoga, CA 95070
(408) 867-1523
Related to:
Willie Steverson
Connected to:
Angie FazioCono Fazio, 103Gianni A Fazio, 66Heather J Fazio, 53Janet D Fazio, 58Vinny FazioAnne M Fazioli, 48Carol L Fazioli, 66Edi Fazlagic, 40Hassan A Fazli, 65

Albert Fazio Phones & Addresses

  • 19900 Douglass Ln, Saratoga, CA 95070 (408) 867-1523
  • 363 Blackwell Dr, Los Gatos, CA 95032 (408) 358-2090
  • Santa Clara, CA
  • Floral Park, NY
  • Middle Island, NY
  • Annandale, VA
  • 19900 Douglass Ln, Saratoga, CA 95070

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: High school graduate or higher

Emails

l***[email protected]

Business Records

Name / Title
Company / Classification
Phones & Addresses
Albert Fazio
Controller
Cuddy & Feder Llp
Legal Services Office
445 Hamilton Ave, White Plains, NY 10601
(914) 761-1300
Albert P Fazio
Secretary,Treasurer
NEW COLUMBIA GARDEN CO., INC

Publications

Us Patents

Integrated Memory Cell And Method Of Fabrication

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US Patent:
6518618, Feb 11, 2003
Filed:
Dec 3, 1999
Appl. No.:
09/454683
Inventors:
Albert Fazio - Los Gatos CA
Krishna Parat - Palo Alto CA
Glen Wada - Fremont CA
Neal Mielke - Los Altos Hills CA
Rex Stone - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2972
US Classification:
257315, 257333, 257336, 257344, 257371, 257387, 257389, 257412
Abstract:
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Integrated Memory Cell And Method Of Fabrication

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US Patent:
6943071, Sep 13, 2005
Filed:
Jun 3, 2002
Appl. No.:
10/162173
Inventors:
Albert Fazio - Los Gatos CA, US
Krishna Parat - Palo Alto CA, US
Glen Wada - Fremont CA, US
Neal Mielke - Los Altos Hills CA, US
Rex Stone - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L021/8238
US Classification:
438201, 438211, 438257, 438692, 257315, 257321
Abstract:
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Mems Probe Based Memory

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US Patent:
7050320, May 23, 2006
Filed:
Dec 23, 2004
Appl. No.:
11/021859
Inventors:
Stefan Lai - Woodside CA, US
Albert Fazio - Saratoga CA, US
Valluri Rao - Saratgoa CA, US
Mike Brown - Phoenix AZ, US
Krishnamurthy Murali - Pleasanton CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 5/06
US Classification:
365 63, 365174, 365201, 36518901, 257414
Abstract:
Briefly, in accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and optionally a memory controller and a storage medium disposed on the integrated circuit where the storage medium includes chalcogenide islands as storage elements. The MEMS layer may include a movable MEMS platform having probes to connect selected chalcogenide islands via positioning of the MEMS platform. A high voltage source disposed external to the memory layer and the MEMS layer may provide a high voltage to a stator electrode on the memory layer and to a rotor electrode on the MEMS platform to control movement of the MEMS platform with respect to the storage medium. The memory device may be utilized in portable electronic devices such as media players and cellular telephones to provide a nonvolatile storage of information.

Flash Memory Cell Having Reduced Floating Gate To Floating Gate Coupling

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US Patent:
7348618, Mar 25, 2008
Filed:
Mar 30, 2005
Appl. No.:
11/095330
Inventors:
Been-jon K. Woo - Saratoga CA, US
Yudong Kim - Santa Clara CA, US
Albert Fazio - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 27/108
H01L 29/76
H01L 29/94
H01L 31/113
US Classification:
257296
Abstract:
According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

Flash Memory Device Of Capable Of Sensing A Threshold Voltage Of Memory Cells On A Page Mode Of Operation

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US Patent:
RE40567, Nov 11, 2008
Filed:
Feb 21, 2002
Appl. No.:
10/080958
Inventors:
Albert Fazio - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/34
US Classification:
36518521, 36518526, 36518512, 36518524, 36518518
Abstract:
A method for determining data stored by a memory cell. The memory cell has a select gate coupled to a wordline, a first electrode coupled to a bitline, and a second electrode coupled to a conductor. The method comprises: floating the bitline; applying a first voltage to the wordline; applying a second voltage to the conductor such that the bitline is set to a third voltage that is equal to the first voltage minus a threshold voltage of the memory cell; and sensing the third voltage to determine the data stored by the memory cell.

Flash Memory Cell Having Reduced Floating Gate To Floating Gate Coupling

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US Patent:
7465625, Dec 16, 2008
Filed:
Oct 17, 2006
Appl. No.:
11/582881
Inventors:
Been-jon K. Woo - Saratoga CA, US
Yudong Kim - Santa Clara CA, US
Albert Fazio - Saratoga CA, US
International Classification:
H01L 21/8234
H01L 21/8244
US Classification:
438238, 438381, 438257, 438692, 257E2117, 257E21006, 257E21165, 257E21278, 257E21293, 257E21304, 257E21645
Abstract:
According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

Data Error Recovery In Non-Volatile Memory

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US Patent:
8291297, Oct 16, 2012
Filed:
Dec 18, 2008
Appl. No.:
12/316986
Inventors:
Richard Coulson - Portland OR, US
Albert Fazio - Saratoga CA, US
Jawad Khan - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 29/00
US Classification:
714764, 714765
Abstract:
When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

Method, Apparatus And System To Determine Access Information For A Phase Change Memory

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US Patent:
8649212, Feb 11, 2014
Filed:
Sep 24, 2010
Appl. No.:
12/890581
Inventors:
Derchang Kau - Cupertino CA, US
Albert Fazio - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/00
US Classification:
365163, 365158, 365171
Abstract:
Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.
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Albert F Fazio from Saratoga, CA, age ~63 Get Report