Ronald C. Carn - Millis MA Donald R. Metz - Ashburnham MA Steven P. Zagama - Boylston MA Robert C. Kirk - Boylston MA Allan R. Kent - Arlington MA Harold A. Read - Burlin MA Barry A. Henry - Penacook NH Charles E. Kaczor - Dudley MA Milton V. Mills - Boston MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1134
US Classification:
371 165
Abstract:
The reliability of a complex electronic system such as a computer interconnect coupler is enhanced by providing diagnostic capabilities in the system so that internal faults will be quickly diagnosed and repaired. To facilitate the repair process and enhance the likelihood that a defective circuit board will be properly repaired before being re-installed, pertinent internal diagnostic information about the defective circuit is stored in a nonvolatile memory on the circuit board for the defective circuit, so that the information will be physically carried to the repair facility along with the defective circuit.
Allan R. Kent - Arlington MA Ronald E. Goodstein - Newton MA Barry A. Henry - Penacook NH
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H04J 302
US Classification:
370 852
Abstract:
A hierarchical arbitration system is especially useful in a computer interconnect coupler having a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added and a hierarchical rotating priority scheme enables the additional channels to have equal priority with the previously existing channels without requiring reprogramming. A ring channel arbitrator is provided for selecting a particular one of the boards during each cycle when a service request is presented and each channel interface board includes a ring channel arbitrator for selecting on the board a particular one of the channels which have presented a service request.
Blocking Message Transmission Or Signaling Error In Response To Message Addresses In A Computer Interconnect Coupler For Clusters Of Data Processing Devices
Ronald C. Carn - Millis MA Donald R. Metz - Ashburnham MA Steven P. Zagame - Boylston MA Robert C. Kirk - Boylston MA Allan R. Kent - Arlington MA Harold A. Read - Burlin MA Barry A. Henry - Penacook NH Charles E. Kaczor - Dudley MA Milton V. Mills - Boston MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H04L 1244
US Classification:
370 60
Abstract:
A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added.
Computer Interconnect Coupler For Clusters Of Data Processing Devices
Allan R. Kent - Arlington MA Harold A. Read - Burlin MA Barry A. Henry - Penacook NH Charles E. Kaczor - Dudley MA Milton V. Mills - Boston MA Ronald C. Carn - Millis MA Donald R. Metz - Ashburnham MA Steven P. Zagame - Boylston MA Robert C. Kirk - Boylston MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H04Q 100
US Classification:
340825160
Abstract:
A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing data to return an acknowledgment responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added.
Ronald C. Carn - Millis MA Donald R. Metz - Ashburnham MA Steven P. Zagame - Boylston MA Robert C. Kirk - Boylston MA Allan R. Kent - Arlington MA Harold A. Read - Burlin MA Barry A. Henry - Penacook NH Charles E. Kaczor - Dudley MA Milton V. Mills - Boston MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H04L 1244
US Classification:
370 941
Abstract:
A computer interconnect coupler has channel transmitters and logic and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an ackowledgement responsive to the incoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added.
Memory For Use In A Computer System In Which Memories Have Diverse Retrieval Characteristics
Alan Kotok - Waltham MA Allan R. Kent - Framingham MA David A. Gross - Stow MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1300
US Classification:
3401725
Abstract:
A memory unit for use with a central processor unit in a data processing system. To retrieve data from the memory unit, the central processor unit energizes an appropriate one of several memory retrieval control signal conductors and memory address signal conductors to initiate a memory cycle during which the memory unit transmits an address acknowledgement signal and data signals back to the central processor unit. The memory unit has a characteristic retrieval interval during which the memory cycle is performed to retrieve data. Each memory retrieval control signal corresponds to a different category of characteristic retrieval interval. When the memory unit transmits the data signals, it transmits a data control signal which is delayed with respect to the address acknowledgement signal by a time interval that is directly related to the characteristic retrieval interval for the memory unit. If a memory unit has a certain characteristic retrieval interval, there also is included a circuit for transmitting a data warning signal a fixed time before the data control signal.
Allan R. Kent - Arlington MA Robert E. Stewart - Stow MA Harold A. Read - Burlin MA Barry A. Henry - Penacook NH Charles E. Kaczor - Dudley MA Milton V. Mills - Boston MA Ronald C. Carn - Millis MA Donald R. Metz - Ashburnham MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H04J 302
US Classification:
370 58
Abstract:
A computer interconnect coupler has a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment code responsive to the imcoming message. To permit incremental expansion of the coupler to accommodate an increased number of channels, additional channel interface boards may be added and a hierarchical rotating priority scheme enables the additional channels to have equal priority with the previously existing channels without requiring reprogramming.
