Andrew K Lai

6876218, Apr 5, 2005

Feb 14, 2003

10/367385

Tuyet Ngoc Simmons - Los Gatos CA, US
Andrew W. Lai - Fremont CA, US

Xilinx, Inc. - San Jose CA

G01R031/28

324763, 324765

A method for accurate testing of the output voltage of an integrated circuit comprises enabling a differential voltage comparator on the integrated circuit to be tested. One input to the differential comparator is set to a reference voltage, and the other input is coupled to a node to be tested. A current load is injected at the node, and the output of the voltage comparator can be used to determine if the integrated circuit performs within the specifications set by a manufacturer.

6944809, Sep 13, 2005

Aug 6, 2002

10/214025

Andrew W. Lai - Fremont CA, US
Randy J. Simmons - San Jose CA, US
Teymour M. Mansour - Sunnyvale CA, US
Vincent L. Tong - Fremont CA, US
Jeffrey V. Lindholm - Longmont CO, US
Jay T. Young - Louisville CO, US
William R. Troxel - Longmont CO, US
Sridhar Krishnamurthy - San Jose CA, US

Xilinx, Inc. - San Jose CA

G01R031/28

714725, 714724

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.

6944836, Sep 13, 2005

Nov 15, 2002

10/295715

Andrew W. Lai - Fremont CA, US

Xilinx, Inc. - San Jose CA

G06F017/50
G06F011/00

716 4, 716 1, 716 5, 714 25, 714 36

Structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD. The re-programmable logic block is tested without using the one-time programmable resources needed for implementing user circuits, by including a multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion of the PLD. In some embodiments, a tester operating at a first and lower clock frequency can be used to test a re-programmable logic block operating at a second and higher clock frequency. In some of these embodiments, the one-time programmable fabric is tested at the first clock frequency.

7007250, Feb 28, 2006

Mar 12, 2003

10/388000

Shekhar Bapat - Cupertino CA, US
Robert W. Wells - Cupertino CA, US
Robert D. Patrie - Scotts Valley CA, US
Andrew W. Lai - Fremont CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50

716 4, 716 16

Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

7187199, Mar 6, 2007

May 24, 2005

11/136114

Andrew W. Lai - Fremont CA, US

Xilinx, Inc. - San Jose CA

H03K 19/173

326 38, 326 41, 714725

Structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD. The re-programmable logic block is tested without using the one-time programmable resources needed for implementing user circuits, by including a multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion of the PLD. In some embodiments, a tester operating at a first and lower clock frequency can be used to test a re-programmable logic block operating at a second and higher clock frequency. In some of these embodiments, the one-time programmable fabric is tested at the first clock frequency.

7219314, May 15, 2007

Apr 1, 2004

10/815483

Steven M. Trimberger - San Jose CA, US
Shekhar Bapat - Cupertino CA, US
Robert W. Wells - Cupertino CA, US
Robert D. Patrie - Scotts Valley CA, US
Andrew W. Lai - Fremont CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50
G06F 11/07
G01R 31/3181
G01R 31/02

716 4, 716 16, 716 18, 714 32, 714 33, 714725, 714742, 324526, 324537

Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics. ” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

7583102, Sep 1, 2009

May 5, 2006

11/429584

Tuyet Ngoc Simmons - Los Gatos CA, US
Andy T. Nguyen - San Jose CA, US
Andrew W. Lai - Fremont CA, US
Randy J. Simmons - San Jose CA, US
Shankar Lakkapragada - San Jose CA, US

XILINX, Inc. - San Jose CA

H03K 19/173

326 38, 326 47, 326 46

Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

7620862, Nov 17, 2009

Sep 8, 2005

11/221438

Andrew Wing-Leung Lai - Fremont CA, US

XILINX, Inc. - San Jose CA

G01R 31/28
G06F 11/00
G06F 1/00

714725, 714 25, 714 47, 714 48, 714 55, 713500

The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.