Search

Blaise A Vignon

from Stanford, CA
Age ~46
Get Report
Related to:
Irene E Vignon, 47
Connected to:
Patricia A Vignona, 64Paul E Vignone, 77Benny R Vigo, 90Dino Vigo, 49Helen C Vigo, 82Martha T Vigo, 80Miguel A Vigo, 55Scott B Vigo, 71Robert A Vigoda, 71Jerry J Vigon, 73

Blaise Vignon Phones & Addresses

  • Stanford, CA

Publications

Us Patents

Variable Performance Rasterization With Constant Effort

View page
US Patent:
7804499, Sep 28, 2010
Filed:
Aug 28, 2006
Appl. No.:
11/467665
Inventors:
Steven E. Molnar - Chapel Hill NC, US
Franklin C. Crow - Portola Valley CA, US
Blaise A. Vignon - Stanford CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 15/30
US Classification:
345423, 345422
Abstract:
The current invention involves new systems and methods for providing variable rasterization performance suited to the size and shape of the primitives being rendered. Portions of pixel tiles that are fully covered by a graphics primitive are encoded and processed by the system as rectangles, rather than expanding to explicit samples. This accelerates the rendering of large primitives without increasing the computation resources used for rasterization. In some embodiments, these fully-covered regions can be rendered compressed without ever expanding into samples.

Edge Evaluation Techniques For Graphics Hardware

View page
US Patent:
8063903, Nov 22, 2011
Filed:
Dec 17, 2007
Appl. No.:
12/002564
Inventors:
Blaise A. Vignon - Stanford CA, US
Franklin C. Crow - Portola Valley CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 17/00
US Classification:
345428, 345427, 345421, 345611, 345613, 345506, 345441, 345442, 345443
Abstract:
The edge evaluation technique, in accordance with one embodiment of the present technology, includes determining a number of edges of a given primitive to be evaluated. The technique also includes sequencing evaluation of a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle. The technique further includes sequencing evaluation of a third edge by the first edge evaluation circuit and a fourth edge by the second edge evaluation circuit during a second clock cycle if three or more edges are to be evaluated.

Conservative Triage Of Polygon Status Using Low Precision Edge Evaluation And High Precision Edge Evaluation

View page
US Patent:
8477134, Jul 2, 2013
Filed:
Jun 30, 2006
Appl. No.:
11/479617
Inventors:
Blaise Vignon - Stanford CA, US
Franklin C. Crow - Portola Valley CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 15/40
US Classification:
345421, 345422
Abstract:
In a raster stage of a graphics processor, a method for using low precision evaluation and high precision evaluation for conservative triage of polygon status. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality of tiles of pixels related to the graphics primitive. The tiles are rasterized at a first level precision to generate a plurality of sub-tiles related to the graphics primitive, wherein the sub-tiles are evaluated against the graphics primitive at each of their respective corners. Each of the sub-tiles not related to the graphics primitive are discarded. The sub-tiles related to the graphics primitive are rasterized at a second level precision.

Tile Based Precision Rasterization In A Graphics Pipeline

View page
US Patent:
20080024497, Jan 31, 2008
Filed:
Jul 26, 2006
Appl. No.:
11/494398
Inventors:
Franklin C. Crow - Portola Valley CA, US
Blaise A. Vignon - Stanford CA, US
International Classification:
G06T 17/00
US Classification:
345428
Abstract:
In a raster stage of a graphics processor, a method for tile based precision rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive at a first level precision to generate a plurality of tiles of pixels. The tiles are then rasterized at a second level precision to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.

Long-Distance Synchronous Bus

View page
US Patent:
7406546, Jul 29, 2008
Filed:
Aug 17, 2005
Appl. No.:
11/206329
Inventors:
Blaise A. Vignon - Stanford CA, US
Sean J. Treichler - Mountain View CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/00
US Classification:
710 33, 710 34, 710 36, 710 52, 710 56, 710 58
Abstract:
One embodiment of a long-distance synchronous bus includes a sending unit and a receiving unit. The sending unit and receiving unit are configured to use credit-based handshaking signals to regulate data flow between themselves. The receiving unit includes a skid buffer for storing data packets received from the sending unit. The sending unit transmits one data packet to the receiving unit for each credit in possession and consumes one credit for each such transmitted data packet. The receiving unit transmits one credit to the sending unit for each data packet that is read out of the skid buffer. In another embodiment, transmitted data may be broadcast to multiple receiving units by routing the data from the sending unit to the multiple receiving units and maintaining separate credit-based handshaking signals for each receiving unit.
Control profile
Blaise A Vignon from Stanford, CA, age ~46 Get Report