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Brian T Vanderpool

from Byron, MN
Age ~49
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Also known as:
Bria Vanderpool, Heather Vanderpool
Phone and address:
5219 Roselee Cir, Byron, MN 55920
(507) 775-7669
Related to:
Richard T Vanderpool, 98Katrina M Meyer, 45Nathan G Meyer, 42William H Meyer, 73Heather L Vanderpool, 48Jill M Dahl, 50Thomas R Vanderpool, 74Keith M Vanderpool, 44Carol J Vanderpool, 75Rebecca R Vanderpool, 42John A Meyer, 78Barbara A Meyer, 76
Connected to:
Alan L Vanderslice, 69Aloijs Vanderriet, 65Bernadette D Vanderpool, 76Bryan Vanderploeg, 45Charles E Vanderpool, 85Clint E Vanderpool, 56Dan N VanderpasDemetrius K Vanderson, 34Elizabeth A Vandersloot, 59Fred A Vandersys, 72

Brian Vanderpool Phones & Addresses

  • 5219 Roselee Cir, Byron, MN 55920 (507) 775-7669
  • 7240 125Th St, Elgin, MN 55932 (507) 876-2481
  • 5612 Silas Dent Rd, Rochester, MN 55901 (507) 252-8242
  • 5878 Hobe Ln, Saint Paul, MN 55110 (651) 426-5900
  • White Bear Lake, MN
  • 2029 Middleton St, Middleton, WI 53562 (608) 831-7051
  • Madison, WI
  • 5612 Silas Dent Rd NW, Rochester, MN 55901 (507) 317-0167

Work

Position: Protective Service Occupations

Education

Degree: High school graduate or higher

Emails

b***[email protected]

Resumes

Resumes

Brian Vanderpool Photo 1

Senior Engineer

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Location:
923 2Nd St, Byron, MN 55920
Industry:
Computer Hardware
Work:
Ibm Jun 2011 - Jun 2012
Chip Architect
Ibm Jun 2011 - Jun 2012
Senior Engineer
Ibm 1999 - Jun 2011
Advisory Engineer
Cae 1993 - 1999
Programmer and Network Administrator
Education:
University of Wisconsin - Madison 1997 - 1999
Master of Science, Masters, Electrical Engineering University of Wisconsin - Madison 1993 - 1997
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science, German Norwegian University of Science and Technology (Ntnu) 1995 - 1995
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Logic Design
Asic
Computer Architecture
Hardware Architecture
Verilog
Debugging
Vhdl
Perl
Vlsi
Soc
Functional Verification
Semiconductors
Fpga
Static Timing Analysis
Rtl Design
Embedded Systems
Languages:
German
Brian Vanderpool Photo 2

Brian Vanderpool

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Industry:
Information Technology And Services
Brian Vanderpool Photo 3

Brian Vanderpool

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Brian Vanderpool

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Brian Vanderpool

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Publications

Us Patents

Sdram Address Error Detection Method And Apparatus

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US Patent:
6754858, Jun 22, 2004
Filed:
Mar 29, 2001
Appl. No.:
09/820436
Inventors:
John Michael Borkenhagen - Rochester MN
Brian T. Vanderpool - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 2900
US Classification:
714720, 714819
Abstract:
Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst.

Read Prediction Algorithm To Provide Low Latency Reads With Sdram Cache

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US Patent:
6801982, Oct 5, 2004
Filed:
Jan 24, 2002
Appl. No.:
10/057444
Inventors:
John M. Borkenhagen - Rochester MN
Brian T. Vanderpool - Rochester MN
Lawrence D. Whitley - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711118, 711119, 711137, 711213
Abstract:
In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Independent Sequencers In A Dram Control Structure

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US Patent:
6836831, Dec 28, 2004
Filed:
Aug 8, 2002
Appl. No.:
10/215404
Inventors:
John Michael Borkenhagen - Rochester MN
Robert Allen Drehmel - Goodhue MN
Brian T. Vanderpool - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1316
US Classification:
711169, 711 5
Abstract:
Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Methods And Systems For Re-Ordering Commands To Access Memory

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US Patent:
7010654, Mar 7, 2006
Filed:
Jul 24, 2003
Appl. No.:
10/625956
Inventors:
Herman L. Blackmon - Rochester MN, US
Joseph A. Kirscht - Rochester MN, US
James A. Marcella - Rochester MN, US
Brian T. Vanderpool - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711158, 711 5, 711105, 711150, 711151, 711154, 711167, 711168
Abstract:
Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Prioritization Of Out-Of-Order Data Transfers On Shared Data Bus

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US Patent:
7392353, Jun 24, 2008
Filed:
Dec 3, 2004
Appl. No.:
11/004199
Inventors:
Wayne Melvin Barrett - Rochester MN, US
Brian T. Vanderpool - Byron MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/18
G06F 9/312
US Classification:
711151, 710 40, 710244, 711118
Abstract:
Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Derivative Performance Counter Mechanism

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US Patent:
7519510, Apr 14, 2009
Filed:
Nov 18, 2004
Appl. No.:
10/992444
Inventors:
Brian Lee Koehler - Rochester MN, US
Brian T. Vanderpool - Byron MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/30
G06F 15/00
G21C 17/00
US Classification:
702186, 702189, 702198, 700 32, 700 90, 714 47, 714699, 716 4
Abstract:
A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

Early Return Indication For Read Exclusive Requests In Shared Memory Architecture

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US Patent:
7536514, May 19, 2009
Filed:
Sep 13, 2005
Appl. No.:
11/225655
Inventors:
Wayne Melvin Barrett - Rochester MN, US
Kenneth Michael Valk - Rochester MN, US
Brian T. Vanderpool - Byron MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/06
US Classification:
711141, 710100
Abstract:
An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.

Patrol Snooping For Higher Level Cache Eviction Candidate Identification

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US Patent:
7577793, Aug 18, 2009
Filed:
Jan 19, 2006
Appl. No.:
11/335765
Inventors:
John Michael Borkenhagen - Rochester MN, US
Brian T. Vanderpool - Byron MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
US Classification:
711133
Abstract:
A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.
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Brian T Vanderpool from Byron, MN, age ~49 Get Report