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Bruce R Michaud

from Milpitas, CA
Age ~61
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Also known as:
Bruce Michaud, Bruce Ray Michaud, Bruce Ray, Ruce Roy Michaud
Related to:
Marilyn Felder, 60James Michaud, 62Tony MichaudKathy Felder, 79Tony Michaud, 57
Connected to:
Ana P Michaud, 49Bridgid J Michaud, 72Cameron V MichaudCharlene R Michaud, 52Christopher A Michaud, 72Craig Michaud, 46Daphnee Michaud, 40Derrick C Michaud, 46Dineen Michaud, 37Dustin Michaud, 45

Bruce Michaud Phones & Addresses

  • Milpitas, CA
  • Los Altos, CA
  • Union City, CA
  • Los Gatos, CA
  • Prospect, ME
  • South Portland, ME
  • Gilroy, CA
  • Greenville, ME
  • Clayton, CA
  • Fremont, CA
  • San Pablo, CA

Work

Company: Nvidia corp Address: 2701 San Tomas Expy, Santa Clara, CA 95050 Phones: (408) 486-2000 Position: Cto Industries: Semiconductors and Related Devices

Resumes

Resumes

Bruce Michaud Photo 1

Senior Manager Of Engineering

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Location:
3165 Bragdon Way, Clayton, CA 94517
Industry:
Computer Hardware
Work:
Nvidia
Senior Manager of Engineering
Bruce Michaud Photo 2

Bruce Michaud

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Bruce Michaud Photo 3

Bruce Michaud

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Skills:
Satellite Communications
Troubleshooting
Wireless
Voip
Telecommunications
Voice Over Ip
Wireless Technologies
Bruce Michaud Photo 4

Bruce Michaud

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Bruce Michaud
CTO
Nvidia Corp
Semiconductors and Related Devices
2701 San Tomas Expy, Santa Clara, CA 95050
Bruce Michaud
CTO
Nvidia Corp
Semiconductors and Related Devices
2701 San Tomas Expy, Santa Clara, CA 95050
Bruce Michaud
CTO
NVIDIA
Computer Hardware · Mfg Semiconductors/Related Devices & Custom Computer Programming · Mfg Semiconductors/Related Devices and Custom Computer Programming · Radio and Television Broadcasting and Wireless Communication · Semiconductor and Related Device Manufacturing · Custom Computer Programming Svcs · Semiconductor Devices (Manufac
2701 San Tomas Expy, Santa Clara, CA 95050
561 E Elliot Rd #195, Chandler, AZ 85225
3535 Monroe St, Santa Clara, CA 95051
2860 San Tomas Expy, Santa Clara, CA 95051
(408) 486-2000, (408) 980-8001, (408) 486-2200, (408) 486-8236

Publications

Us Patents

Quick-Connect Thermal Solution For Computer Hardware Testing

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US Patent:
7126826, Oct 24, 2006
Filed:
Oct 6, 2004
Appl. No.:
10/960350
Inventors:
George A. Sorensen - Fremont CA, US
Bruce R. Michaud - Clayton CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H05K 7/20
US Classification:
361719, 361704, 361707, 257718, 257719, 165 803
Abstract:
The present invention represents a significant advancement in the field of thermal solutions for computer hardware. In one embodiment, a quick-connect system for cooling a heat-generating electronic device is provided. The electronic device is mounted to a first side of a circuit board. The system includes a first plate having an opening and configured to be coupled to the first side of the circuit board. The system further includes a second plate disposed within the opening and coupled to the first plate with a first suspension system, wherein the first suspension system is configured to enable the second plate to be disposed substantially flat against the electronic device when the first plate is coupled to the first side of the circuit board. The system further includes a cooling module thermally coupled to the second plate and configured to dissipate heat transferred from the electronic device to the second plate.

Design And Method For Plating Pci Express (Pcie) Edge Connector

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US Patent:
7192312, Mar 20, 2007
Filed:
Apr 30, 2004
Appl. No.:
10/836576
Inventors:
Bruce Michaud - Clayton CA, US
Peter Ammann - San Jose CA, US
George Sorensen - Fremont CA, US
International Classification:
H01R 24/00
US Classification:
439633
Abstract:
Embodiments of methods and apparatus for plating a PCI Express edge connector are described. In one embodiment a printed circuit board having connectors is employed for electroplating one or more of the connectors formed thereon. The printed circuit board comprises a substrate having one or more layers, and a plurality of connectors formed on one or more of the layers, wherein at least one connector includes at least one short pin and at least one extra pin. The at least one extra pin extends beyond an outer shape of the printed circuit board after fabrication. The printed circuit board also includes connection circuitry formed on one or more of the layers, wherein the connection circuitry is configured to electrically connect the short pin with the extra pin at least during electroplating of said short pin.

Design And Method For Plating Pci Express (Pcie) Edge Connector

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US Patent:
7341490, Mar 11, 2008
Filed:
Feb 6, 2007
Appl. No.:
11/671909
Inventors:
Bruce Michaud - Clayton CA, US
Peter Ammann - San Jose CA, US
George Sorensen - Fremont CA, US
International Classification:
H01R 24/00
US Classification:
439633
Abstract:
Embodiments of methods and apparatus for plating a PCI Express edge connector are described. In one embodiment, a printed circuit board having connectors is employed for electroplating one or more of the connectors formed thereon. The printed circuit board comprises a substrate having one or more layers, and a plurality of connectors formed on one or more of the layers, wherein at least one connector includes at least one short pin and at least one extra pin. The at least one extra pin extends beyond an outer shape of the printed circuit board after fabrication. The printed circuit board also includes connection circuitry formed on one or more of the layers, wherein the connection circuitry is configured to electrically connect the short pin with the extra pin at least during electroplating of said short pin.

Design And Method For Plating Pci Express (Pcie) Edge Connector

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US Patent:
7534145, May 19, 2009
Filed:
Dec 7, 2006
Appl. No.:
11/636301
Inventors:
Bruce Michaud - Clayton CA, US
Peter Ammann - San Jose CA, US
George Sorenson - Fremont CA, US
Assignee:
nVidia Corporation - Santa Clara CA
International Classification:
H01R 24/00
US Classification:
439633
Abstract:
Embodiments of methods and apparatus for plating a PCI Express edge connector are described. In one embodiment, a printed circuit board having connectors is employed for electroplating one or more of the connectors formed thereon. The printed circuit board comprises a substrate having one or more layers, and a plurality of connectors formed on one or more of the layers, wherein at least one connector includes at least one short pin and at least one extra pin. The at least one extra pin extends beyond an outer shape of the printed circuit board after fabrication. The printed circuit board also includes connection circuitry formed on one or more of the layers, wherein the connection circuitry is configured to electrically connect the short pin with the extra pin at least during electroplating of said short pin.
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Bruce R Michaud from Milpitas, CA, age ~61 Get Report