Cecil Hertz Kaplinsky

54246547, Jun 13, 1995

Sep 22, 1994

8/310437

Cecil H. Kaplinsky - Palo Alto CA

H03K 19094

326 40

A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output polarity. This programmable macrocell circuit has two master latch elements and one slave latch element. The master latch elements are respectively inverting and noninverting latches which are located on two parallel alternate paths. A set of pass transistors on the input end of the two paths causes an input signal to drive only a selected one of the two paths and its associated master latch element. A two-by-one multiplexer connects the output of the selected master latch element in one of the two signal paths to the input of the slave latch. The control signals for the set of pass transistors and the two-by-one multiplexer can be either clock signals or fixed logic level signals, the particular choice of signals determining whether the circuit operates as a flip-flop, latch, or transparent circuit, and the particular choice of signal paths determining the circuit's output polarity.

RE344443, Nov 16, 1993

Jul 3, 1991

7/725353

Cecil H. Kaplinsky - Palo Alto CA

Xilinx, Inc. - San Jose CA

H04Q 100

3408258

A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external world when certain preselected events happen.

51310813, Jul 14, 1992

Mar 23, 1989

7/327845

Craig A. MacKenna - Los Gatos CA
Cecil H. Kaplinsky - Palo Alto CA

North American Philips Corp., Signetics Div. - Sunnyvale CA

G06F 1312
G06F 1310

395275

An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon. The I/O processor and I/O controllers may be interconnected with a local external memory via a local bus which is selectively coupled with a system bus interconnecting the main processor unit and main external memory.

57962685, Aug 18, 1998

Oct 2, 1996

8/723615

Cecil H. Kaplinsky - Palo Alto CA

H03K 19177

326 39

A programmable logic device in accordance with the present invention includes a partially populated switch matrix for coupling a plurality of logic blocks. Having a partial switch matrix reduces the silicon area requirement of the device. In addition, the capacitive loading is reduced, which improves propagation speed and lowers the power requirement of the sense amps, since smaller sense amps can be used. Bypass means are provided to allow the propagation bit lines (i. e. carry and shift lines) to bypass one or more logic block. Each of the logic blocks includes a plurality of logic cells. Means are provided among the logic cells to provide bypass capability for the propagation lines among the logic cells. The logic cells feature means for reverse propagation of the carry and shift bits among the logic cells. The logic cells of the present invention also feature reverse propagation with bypass.

54883229, Jan 30, 1996

Aug 29, 1994

8/297641

Cecil H. Kaplinsky - Palo Alto CA

H03K 5153

327 74

A buffer, driver, or level-shifting circuit having an input connected to signal inputs of a pair of comparators and an output connected between a pair of pull-up and pull-down transistors controlled by the comparators. A first reference voltage applied to the reference input of the comparator controlling the pull-up transistor is selected to be less than the nominal transition point of the circuit, while a second reference voltage applied to the reference input of the comparator controlling the pull-down transistor is selected to be greater than the nominal transition point of the circuit, thereby allowing the circuit to recognize the beginning of signal transitions on the its input sooner. The comparators are differential amplifiers which are enableable and disableable in response to a feedback signal from the circuit's output in order to reduce current consumption during transitions. When the output is high, the comparator controlling pull-down is enabled, while the comparator controlling pull-up is disabled.

59202106, Jul 6, 1999

Nov 21, 1996

8/754755

Cecil H. Kaplinsky - Palo Alto CA

H03K 5153
H03K 19017

327112

A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

50121359, Apr 30, 1991

May 12, 1989

7/351437

Cecil H. Kaplinsky - Palo Alto CA

Plus Logic, Inc. - Santa Clara CA

H03K 19094

307465

Apparatus for programming an OR gate, an AND gate or an EXCLUSIVE-OR gate to accept or not accept an input signal at an input terminal of the gate. The apparatus includes two pass transistors, a source of high or low voltage depending on the gate to be programmed, and a control signal that is used for programming the gates of the pass transistors. The two pass transistors may be of the same channel type i. e. ,. both n-channel or both p-channel, or they may be of opposite channel types. This apparatus provides positive input signals from a group of input signals to avoid voltage signal ambiguities in programming the gates. Use of these programmable gates in combination in an AND-OR array is illustrated.

50288210, Jul 2, 1991

Mar 1, 1990

7/487750

Cecil H. Kaplinsky - Palo Alto CA

Plus Logic, Inc. - San Jose CA

H03K 19177

307465

A programmable logic device having a plurality of functional units, a programmable interconnect matrix for connecting the functional units together, input and output pins coupled to the interconnect matrix, and programmable inverters connected between the pins and conductive lines of the matrix to permit external signals leading into or out of the interconnect matrix to be inverted, if desired. Each functional unit may itself be a programmable logic device with inputs, an AND array connected to the inputs, an OR array connected to the AND array, optional registers and inverters on the output side of the OR array, and outputs coupled to the OR array, the registers or the inverters. The programmable interconnect matrix includes two sets of conductive lines crossing one another and connectable by programmable links at each intersection. The lines connect to functional unit inputs and to input and output pins.