20080155490, Jun 26, 2008
Tianwen Tang - Fremont CA, US
Raghunath Vutukuru - San Jose CA, US
Chao-Cheng Yeh - Fremont CA, US
Methods for reducing coupling noise, reducing signal skew, and saving layout area for an integrated circuit. Aspects of one method may include prioritizing a plurality of clock signals for layout on a chip. The clock signals may comprise functional and test clock signals and test clock signals, where the functional and test clock signals may not both be active at the same time. The clock signals may be routed based on the prioritization, where the priority may be based on, for example, frequency and/or slew rate of each clock signal. A route guide may also be used to take into account an amount of cross-talk reduction desired for each clock signal and/or whether a metal layer may be used may also be used in routing the clock signals. The clocks signals may also be routed so that the functional clock signals may be interlaced with the test clock signals.