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Cheng-Yeh Yen

from Redwood City, CA
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Related to:
Ryan Yen, 28Miaohsun YenStephanie YenHsuehmei YenCheng Yeh Yen, 58
Connected to:
Bonnie C Yen, 44Bonny C Yen, 84Caleb Yen, 33Chi K Yen, 38Chris YenChua YenDwight Yen, 72Elton Yen, 65Gail Yen, 33Giai V Yen, 62

Cheng-Yeh Yen Phones & Addresses

  • 819 Southport Dr, Redwood City, CA 94065 (650) 743-6527

Resumes

Resumes

Cheng-Yeh Yen Photo 1

User Interface Engineering Manager

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Location:
819 Southport Dr, Redwood City, CA 94065
Industry:
Computer Software
Work:
Synopsys
User Interface Engineering Manager
Reshape Feb 2003 - Apr 2005
Senior Software Engineer
Electroglas May 2001 - Jul 2002
Software Development Manager
123Signup Aug 1999 - Mar 2001
Development Manager
Knights Technology Oct 1998 - Jul 1999
Cad and Nav Manager
Education:
The Ohio State University 1990 - 1992
Masters, Master of Science In Electrical Engineering National Taiwan University 1984 - 1988
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Xml
Software Development
Windows
Java
C
Html
Perl
Shell Scripting
Servlets
Unix
Qt
Visual C++
Software Engineering
User Interface
Debugging
Interests:
Boating
Kids
Cooking
Investing
Traveling
Outdoors
Electronics
Home Improvement
Shooting
Reading
Sports
Travel
Home Decoration
Languages:
English
Cheng-Yeh Yen Photo 2

Cheng-Yeh Yen

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Location:
San Francisco Bay Area
Industry:
Computer Software
Skills:
HTML
XML
Java

Publications

Us Patents

Flow Definition Language For Designing Integrated Circuit Implementation Flows

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US Patent:
7353488, Apr 1, 2008
Filed:
May 27, 2004
Appl. No.:
10/856268
Inventors:
Mike Coffin - San Jose CA, US
Peter Dahl - Sunnyvale CA, US
Cheng-yeh Yen - Redwood City CA, US
Assignee:
Magma Design Automation, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 17/00
G06F 3/00
G06F 9/44
US Classification:
716 18, 707100, 717132, 715700
Abstract:
An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.
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Cheng-Yeh Yen from Redwood City, CA Get Report