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Christopher Scerbo Phones & Addresses

  • 1191 Morris Park Ave, Bronx, NY 10461
  • 2933 Middletown Rd, Bronx, NY 10461

Publications

Us Patents

Silicidation Of Device Contacts Using Pre-Amorphization Implant Of Semiconductor Substrate

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US Patent:
20130049200, Feb 28, 2013
Filed:
Aug 30, 2012
Appl. No.:
13/598686
Inventors:
Paul R. Besser - Sunnyvale CA, US
Roy A. Carruthers - Stormville NY, US
Christopher P. D'Emic - Ossining NY, US
Christian Lavoie - Pleasantville NY, US
Conal E. Murray - Yorktown Heights NY, US
Kazuya Ohuchi - Kanagawa, JP
Christopher Scerbo - Bronx NY, US
Bin Yang - San Carlos CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/43
US Classification:
257741, 257E29146
Abstract:
Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to fond an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A silicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

Silicidation Of Device Contacts Using Pre-Amorphization Implant Of Semiconductor Substrate

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US Patent:
20130049199, Feb 28, 2013
Filed:
Aug 31, 2011
Appl. No.:
13/222469
Inventors:
Paul R. Besser - Sunnyvale CA, US
Roy A. Carruthers - Stormville NY, US
Christopher P. D'Emic - Ossining NY, US
Christian Lavoie - Pleasantville NY, US
Conal E. Murray - Yorktown Heights NY, US
Kazuya Ohuchi - Kanagawa, JP
Christopher Scerbo - Bronx NY, US
Bin Yang - San Carlos CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/532
H01L 21/336
H01L 21/768
US Classification:
257741, 438682, 438305, 257E21575, 257E21409, 257E23157
Abstract:
Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

Self-Aligned Trench Metal-Alloying For Iii-V Nfets

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US Patent:
20190311945, Oct 10, 2019
Filed:
Jun 17, 2019
Appl. No.:
16/443283
Inventors:
- Armonk NY, US
Sebastian U. Engelmann - White Plains NY, US
Marinus Johannes Petrus Hopstaken - Carmel NY, US
Christopher Scerbo - Bronx NY, US
Hongwen Yan - Somers NY, US
Yu Zhu - Yorktown Heights NY, US
International Classification:
H01L 21/768
H01L 21/223
H01L 23/535
H01L 29/66
H01L 29/20
H01L 29/78
H01L 21/285
H01L 21/28
Abstract:
After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Self-Aligned Trench Metal-Alloying For Iii-V Nfets

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US Patent:
20180096885, Apr 5, 2018
Filed:
Oct 4, 2016
Appl. No.:
15/284956
Inventors:
- Armonk NY, US
Sebastian U. Engelmann - White Plains NY, US
Marinus Johannes Petrus Hopstaken - Carmel NY, US
Christopher Scerbo - Bronx NY, US
Hongwen Yan - Somers NY, US
Yu Zhu - West Harrison NY, US
International Classification:
H01L 21/768
H01L 23/535
H01L 29/08
H01L 29/20
H01L 29/207
H01L 29/66
H01L 21/02
Abstract:
After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Iii-V Extension By High Temperature Plasma Doping

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US Patent:
20170373149, Dec 28, 2017
Filed:
Jun 28, 2016
Appl. No.:
15/195107
Inventors:
- Armonk NY, US
Kevin K. Chan - Staten Island NY, US
Sebastian U. Engelmann - White Plains NY, US
Renee T. Mo - Yorktown Heights NY, US
Christopher Scerbo - Bronx NY, US
Hongwen Yan - Somers NY, US
Jeng-Bang Yau - Yorktown Heights NY, US
International Classification:
H01L 29/10
H01L 21/223
H01L 21/02
H01L 29/78
H01L 29/207
Abstract:
A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.
Christopher L Scerbo from Bronx, NY, age ~46 Get Report