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Clarence B Coffee

from Pembroke Pines, FL
Age ~37
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Also known as:
Clarence B Coffe, Clarence Cofee, Coffee I Clarence, B Coffee Clarence
Related to:
Tiffany Coffee RogersKathleen M Rogers, 99Joy L Coffee, 61Kimberly A Rogers, 37Katrina Y Coffee, 48Sandy CoffeeGladys T Coffee, 67Elizabeth Coffee, 69Sandra S Rogers, 64Matthew K Rogers, 39Andrea CoffeeMariko Coffee, 52Sandricka Coffee, 50Elizabeth G Johnson, 70
Connected to:
Break Coffee, 56Cara E Coffee, 45Cindy M Coffee, 58Jenny Coffee, 44Liz CoffeePhillip D Coffee, 61Shondria D Coffee, 46Tammie G Coffee, 58William G Coffee, 57Caldonia C Coffeey, 78

Clarence Coffee Phones & Addresses

  • Pembroke Pines, FL
  • North Hollywood, CA
  • Burbank, CA
  • Aventura, FL
  • Los Angeles, CA

Work

Company: The employment guide, llc Position: Account executive

Industries

Staffing And Recruiting

Resumes

Resumes

Clarence Coffee Photo 1

Account Executive

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Location:
4460 Corporation Ln, Virginia Beach, VA 23462
Industry:
Staffing And Recruiting
Work:
The Employment Guide, Llc
Account Executive

Business Records

Name / Title
Company / Classification
Phones & Addresses
Clarence Coffee
Principal, Managing
Cojo Worldwide, LLC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
1269 NW 159 Ln, Hollywood, FL 33028

Publications

Us Patents

System And Method For Concurrently Requesting Input/Output And Memory Address Space While Maintaining Order Of Data Sent And Returned Therefrom

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US Patent:
6356972, Mar 12, 2002
Filed:
Jan 19, 2001
Appl. No.:
09/765773
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Information Technologies Group, LP - Houston TX
International Classification:
G06F 1314
US Classification:
710310
Abstract:
A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue.

Performing An N-Bit Write Access To An M×N-Bit-Only Peripheral

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US Patent:
7376777, May 20, 2008
Filed:
Sep 23, 2005
Appl. No.:
11/233915
Inventors:
Clarence K. Coffee - Pembroke Pines FL, US
Eytan Hartung - Boca Raton FL, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/36
G06F 13/12
G06F 13/40
US Classification:
710306, 710 35, 710 65, 710 66, 710307, 710311
Abstract:
A system-on-chip () includes a 16-bit DSP (), a 16-bit data bus () coupled to the DSP, at least one 32-bit-only peripheral (), a 32-bit data bus () coupled to the peripheral, and a bridge (), including a write merge system (), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure ( and ), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

System And Method For Improving Processor Read Latency In A System Employing Error Checking And Correction

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US Patent:
6272651, Aug 7, 2001
Filed:
Aug 17, 1998
Appl. No.:
9/135274
Inventors:
Kenneth T. Chin - Cypress TX
Clarence Kevin Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert Allen Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corp. - Houston TX
International Classification:
G06F 1100
US Classification:
714 43
Abstract:
A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads.

System And Method For Aligning An Initial Cache Line Of Data Read From An Input/Output Device By A Central Processing Unit

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US Patent:
6199118, Mar 6, 2001
Filed:
Aug 18, 1998
Appl. No.:
9/135703
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 300
US Classification:
710 1
Abstract:
A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i. e. , target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order.

System And Method For Suppressing Processor Cycles To Memory Until After A Peripheral Device Write Cycle Is Acknowledged By The Memory Arbiter

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US Patent:
62090526, Mar 27, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/164194
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F13/00
US Classification:
710109
Abstract:
A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i. e. , PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus.

System And Method For Aligning An Initial Cache Line Of Data Read From Local Memory By An Input/Output Device

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US Patent:
6160562, Dec 12, 2000
Filed:
Aug 18, 1998
Appl. No.:
9/135620
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1314
US Classification:
345520
Abstract:
A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i. e. , target address) is not the first address (i. e. , initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit.

System And Method For Optimally Deferring Or Retrying A Cycle Upon A Processor Bus That Is Destined For A Peripheral Bus

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US Patent:
62161903, Apr 10, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/164192
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1342
US Classification:
710128
Abstract:
A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the peripheral bus and memory bus. Those cycles can be arranged in order within the CPU bus pipeline. A subset of cycles destined for a peripheral bus can be stalled within a snoop phase associated with the CPU bus. Snoop stall can continue until a memory cycle is encountered upon the CPU bus pipeline within a phase prior to the snoop phase. Once the memory cycle progresses to the snoop phase, snoop stall can be discontinued and the previous, peripheral cycles can then be deferred and/or retried, allowing the memory cycle to be quickly dispatched through all phases of the CPU bus and onto the memory bus. In this fashion, memory cycles can be completed quickly, yet deferrals or retries are minimized to avoid the throughput penalty associated with deferring or retrying cycles back again through each phase of the CPU bus.

System And Method For Concurrently Requesting Input/Output And Memory Address Space While Maintaining Order Of Data Sent And Returned Therefrom

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US Patent:
6202101, Mar 13, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/164189
Inventors:
Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
710 5
Abstract:
A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue.
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Clarence B Coffee from Pembroke Pines, FL, age ~37 Get Report