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Dale C Main

from La Canada Flintridge, CA
Age ~61
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Also known as:
Dale Charles Main
Phone and address:
753 Saint Katherine Dr, La Canada, CA 91011
(818) 517-4732
Related to:
Zachary T MainAthene M Main, 92
Connected to:
Aj MainBradley R Main, 72Bud Main, 79Dean C Main, 58Dick L Main, 62Felix W Main, 87Heike E Main, 51Jacqueline S Main, 38Kelli Main, 54Kevan L Main, 71

Dale Main Phones & Addresses

  • 753 Saint Katherine Dr, La Canada Flintridge, CA 91011 (818) 517-4732
  • La Canada, CA
  • Thousand Oaks, CA
  • Solana Beach, CA
  • Addy, WA
  • Mammoth Lakes, CA
  • La Canada Flt, CA

Work

Company: Micro/sys, inc. Address: 3730 Park Pl, Montrose, CA 91020 Phones: (818) 244-4600 Position: Harwdare engineer Industries: Electronic Computers

Business Records

Name / Title
Company / Classification
Phones & Addresses
Dale Main
Harwdare Engineer
Micro/Sys, Inc.
Electronic Computers
3730 Park Pl, Montrose, CA 91020
Dale Main
Harwdare Engineer
Micro/Sys, Inc.
Electronic Computers
3730 Park Pl, Montrose, CA 91020
Dale Main
Harwdare Engineer
MICRO/SYS, INC
Other Computer Peripheral Equip Mfg · Electronic Computers
3730 Park Pl, Montrose, CA 91020
(818) 244-4600, (818) 244-4246

Publications

Us Patents

Method And Apparatus For Optically Reading Gas Sampling Test Cards

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US Patent:
20080259341, Oct 23, 2008
Filed:
Nov 6, 2007
Appl. No.:
11/935881
Inventors:
Gary W. Short - Glendale CA, US
Dale Main - La Canada CA, US
Margaret R. Pippin - Yorktown VA, US
Linda Bush - Lawrence KS, US
International Classification:
G01N 21/84
US Classification:
356437
Abstract:
A method and apparatus for measuring a gas concentration detected by a passive sampler are provided. The apparatus includes a light source which illuminates a passive sampler, a detector which detects light from the light source reflected from the passive sampler and provides an output signal, and a microprocessor which receives the output signal and calculates light absorption by the passive sampler based on the received signal.

Methods And Systems Stackable Circuit Boards

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US Patent:
7748992, Jul 6, 2010
Filed:
Jan 30, 2008
Appl. No.:
12/022990
Inventors:
Susan Wooley - Montrose CA, US
Glenn S. Kubota - Montrose CA, US
Dale Main - Montrose CA, US
Assignee:
Micro/Sys, Inc. - Montrose CA
International Classification:
H01R 12/00
US Classification:
439 74, 439660
Abstract:
The present invention is directed toward methods and systems for providing a stackable connector system comprising a switching device configured to select a signal based on a location of a first circuit board above or below a second circuit board. A sense line may be coupled to a location signal and configured to indicate if the first circuit board is above or below the second circuit board. Additionally, a first connector, including a first conductor element, may be located on the first circuit board and a second connector, including a second conductor element, may be located on the first circuit board. An electrical connection element on the first circuit board mat connect the first conductor element to the second conductor element, wherein the location of the first conductor element in the first connector is offset relative to the location of the second conductor element in the second connector.

Device-Based Search In Data Storage Device

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US Patent:
20190294730, Sep 26, 2019
Filed:
Nov 19, 2014
Appl. No.:
14/547500
Inventors:
- Irvine CA, US
DALE C. MAIN - LA CANADA-FLINTRIDGE CA, US
International Classification:
G06F 17/30
Abstract:
Systems and methods are disclosed for distributed searching in a data storage system. A data storage device may include a volatile memory module, a non-volatile memory module and control circuitry configured to perform a search on data stored in the non-volatile memory module according to search criteria. The control circuitry is further configured to store search results associated with the search in one or more of the volatile memory module and the non-volatile memory module and provide at least a portion of the search results to a host system.

Host Configured Multi Serial Interface Device

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US Patent:
20180225252, Aug 9, 2018
Filed:
Apr 10, 2018
Appl. No.:
15/949355
Inventors:
- San Jose CA, US
Dale Charles Main - La Canada-Flintridge CA, US
International Classification:
G06F 13/42
G06F 13/38
G06F 13/40
Abstract:
A dynamically configurable device including a connector configured to detect a first status of an interface selection mechanism, and a first Serializer De-serializer (SerDes) configured to drive a first selected interface from among a plurality of interfaces based on the first status. In response to the first status having a first state, the first selected interface is a first interface that causes the dynamically configurable device to present as a first type of device, and in response to the first status having a second state, the first selected interface is a second interface that causes the dynamically configurable device to present as a second type of device.

Memory Interface Initialization With Precessor In Reset

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US Patent:
20180143841, May 24, 2018
Filed:
Jan 18, 2018
Appl. No.:
15/874165
Inventors:
- Irvine CA, US
DALE C. MAIN - LA CANADA-FLINTRIDGE CA, US
International Classification:
G06F 9/4401
G06F 3/06
Abstract:
A device comprises control circuitry including a processor, a memory interface, memory interface initialization circuitry, and non-volatile storage storing initialization parameters for initializing the memory interface. The control circuitry is configured to, while the processor is held in reset, initialize the memory interface using the initialization parameters and the memory interface initialization circuitry, after the memory interface has been initialized, receive instructions from a non-volatile memory module over the memory interface, and, after the processor has been released from reset, execute the instructions using the processor.

Read Disturb Compensation Using Weighted Programming Patterns

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US Patent:
20170300256, Oct 19, 2017
Filed:
Jul 4, 2017
Appl. No.:
15/641258
Inventors:
- San Jose CA, US
DALE CHARLES MAIN - LA CANADA-FLINTRIDGE CA, US
International Classification:
G06F 3/06
G11C 16/10
G11C 11/56
G06F 3/06
G11C 7/10
G06F 3/06
G11C 16/34
G11C 11/56
Abstract:
A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller. The controller is configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by receiving or accessing data to be written to the solid-state non-volatile memory, encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state, and writing the encoded data to the solid-state non-volatile memory.

Temperature-Based Data Refreshing

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US Patent:
20170257940, Sep 7, 2017
Filed:
May 23, 2017
Appl. No.:
15/602725
Inventors:
- Irvine CA, US
Dean Mitcham JENKINS - La Canada-Flintridge CA, US
Dale Charles MAIN - La Canada-Flintridge CA, US
International Classification:
H05K 1/02
G11C 16/34
G11C 7/04
G11C 16/10
G11B 5/09
Abstract:
Systems and methods are disclosed for managing temperature in a data storage device. A data storage device includes non-volatile solid-state memory, a temperature sensor, a heating device, and a controller. The controller is configured to receive a temperature signal from the temperature sensor indicating a temperature of at least a portion of the data storage device, determine that the temperature is below a first predetermined threshold, activate the heating device to increase the temperature of the at least a portion of the data storage device, and write data associated with a write command to the non-volatile solid-state memory.

Weighted Programming Patterns In Solid-State Data Storage Systems

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US Patent:
20170090785, Mar 30, 2017
Filed:
Sep 24, 2015
Appl. No.:
14/864653
Inventors:
- Irvine CA, US
DALE CHARLES MAIN - LA CANADA-FLINTRIDGE CA, US
International Classification:
G06F 3/06
G11C 16/34
G11C 11/56
Abstract:
Systems and methods are disclosed for programming data in non-volatile memory arrays. A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller configured to improve data retention or reduce read disturb of at least a portion of the solid-state non-volatile memory at least in part by receiving data to be written to the solid-state non-volatile memory. The controller is further configured to, when a data retention programming mode is set, encode the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower voltage level than the second programming state, and write the encoded data to the solid-state non-volatile memory. When a read disturb programming mode is set, the first programming state is associated with a higher voltage level than the second programming state.
Control profile
Dale C Main from La Canada Flintridge, CA, age ~61 Get Report