Daniel J Kolor

6434731, Aug 13, 2002

Oct 26, 1999

09/427301

Thomas Charles Brennan - Rochester MN
Kevin Charles Gower - LaGrangeville NY
Daniel John Kolor - Wappingers Falls NY
Erik Victor Kusko - Hopewell Junction NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 10

An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas. Thus, skew is minimized during the automated placement of the design of the signal distribution network.

6470417, Oct 22, 2002

Jun 12, 2000

09/592525

Daniel J. Kolor - Wappingers Falls NY
Scott J. Hadderman - Pleasant Valley NY

International Business Machines Corporation - Armonk NY

G06F 1202

711105

A current generation, quad RAS, single CAS, stacked component ( ) including four 4 MbÃ4 bits 11/11 DRAMs ( ) is arranged to emulate a next generation 16 MbÃ4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller ( ) includes a row address of 12 bits and a column address of 12 bits. Each DRAM ( ) within the current generation DRAM component ( ) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic ( ). The additional row address bit is decoded by the decoding logic ( ) to direct the RAS signals over two of the four RAS lines ( ), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic ( ) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line ( ) directs the CAS signal to all of the stacked DRAMs ( ).

6470458, Oct 22, 2002

Jul 29, 1999

09/363951

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Daniel John Kolor - Wappingers Falls NY
Bradley McCredie - Austin TX

International Business Machines Corporation - Armonk NY

G06F 112

713400, 713 1, 713500, 713600

A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chips clock phase as a reference clock phase for the secondary chips.

8463952, Jun 11, 2013

Aug 4, 2011

13/198641

Allen E. Tracht - Pittsburgh PA, US
Daniel J. Kolor - Cranberry Township PA, US
W. Leo Rollins - Cheswick PA, US

NetApp, Inc. - Sunnyvale CA

G06F 11/00
G06F 3/00

710 14, 710 38, 714 2

A first device port and a second device port are connected using a first cable and a second cable. The first device port and the second device port use a divisible number of lanes, X for communication. The first cable uses X′ lanes, where X′ is less than X. The second cable uses X-X′ lanes, where X-X′ is also less than X. If the first cable is disconnected or fails, then the second cable is used after a failover operation.

20070088917, Apr 19, 2007

Oct 14, 2005

11/250538

Samantha Ranaweera - Cranberry Township PA, US
Daniel Kolor - Cranberry Township PA, US

G06F 12/00

711148000

A system and method creates and maintains a serial attached SCSI (SAS) logical communication channel among a plurality of storage systems. The storage systems utilize a SAS expander to form a SAS domain comprising a plurality of storage systems and/or storage devices. A target mode module and a logical channel protocol module executing on each storage system enable storage system to storage system messaging via the SAS domain.

55900712, Dec 31, 1996

Nov 16, 1995

8/559321

Daniel J. Kolor - Wappingers Falls NY
Nitin B. Gupte - Hopewell Junction NY
Siddharth R. Shah - Hopewell Junction NY

International Business Machines Corporation - Armonk NY

G11C 1124

365149

A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.

60943971, Jul 25, 2000

Feb 9, 1999

9/246465

Scott J. Hadderman - Pleasant Valley NY
Daniel J. Kolor - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G11C 800

36523003

A method and apparatus for addressing multi-bank memory. The method includes generating a first bank select and generating a first row address. The first row address is stored and presented as a second bank select during an activate portion of the memory cycle. During an access portion of the memory cycle, a first bank select is generated and the saved second bank select is retrieved from storage. The first bank select and retrieved second bank select identify a bank of memory. The apparatus includes a storage device for saving the second bank select. The second bank select may be stored based on the value of the first bank select.

20200052955, Feb 13, 2020

Nov 14, 2018

16/190705

- Sunnyvale CA, US
Daniel John Kolor - Cranberry Township PA, US

H04L 12/24
H04L 12/931
H04L 12/935

Techniques are provided for dual port storage device emulation. A switch is configured with a first virtual switch to provide a first computing device with access a first single port device through a first port and a second port. The switch is configured with a second virtual switch to provide a second computing device with access to a second single port device through a third port and a fourth port. In response to determining that the first computing device has experienced a failure, the first virtual switch and the second virtual switch are reconfigured to provide the second computing device with access to the first single port device through the second port and access to the second single port device through the fourth port. The first computing device is disconnected from accessing the first single port device through the first virtual switch.