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Darren C Cronquist

from San Francisco, CA
Age ~53
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Also known as:
Darren Charles Cronquist
Phone and address:
4348 17Th St, San Francisco, CA 94114
(415) 431-1688
Related to:
Decedents CronquistDiana L Cronquist, 56Linda Cronquist, 82Richard Cronquist
Connected to:
Laura D Cronshey, 41Lori R Cronyn, 73Jonathan M Croog, 46Amy N Crook, 45Angelina Crook, 50Brigitte D Crook, 48Cherry Crook, 32Darla M Crook, 60Daryl L Crook, 52Debra L Crook, 63

Darren Cronquist Phones & Addresses

  • 4348 17Th St, San Francisco, CA 94114 (415) 431-1688
  • 4614 18Th St, San Francisco, CA 94114 (415) 431-1688
  • 4614B 18Th St, San Francisco, CA 94114
  • 4018 19Th St, San Francisco, CA 94114 (415) 431-1688
  • 1108 Dolores St, San Francisco, CA 94110 (415) 285-4694
  • 1614 Summit Ave, Seattle, WA 98122 (206) 726-8216
  • Coronado, CA
  • 1411 Commodore Pl, Tempe, AZ 85283 (480) 820-7075 (480) 839-0791

Resumes

Resumes

Darren Cronquist Photo 1

Darren Cronquist

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Location:
San Francisco Bay Area
Industry:
Computer Software
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Darren Cronquist

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Publications

Us Patents

System And Method For Creating Systolic Solvers

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US Patent:
7086038, Aug 1, 2006
Filed:
Oct 7, 2002
Appl. No.:
10/266720
Inventors:
Darren C. Cronquist - San Francisco CA, US
Michael S. Schlansker - Los Altos CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/45
US Classification:
717136, 717150, 717151
Abstract:
One embodiment of the invention is a method for forming a solver for a loop nest of code, the method comprising forming a time and space mapping of a portion of the loop nest, performing at least one optimization that is dependent on the time and space mapping to the portion of the loop nest, and forming a solver from the optimized portion of the loop nest.

System And Method For Reducing Wire Delay Or Congestion During Synthesis Of Hardware Solvers

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US Patent:
7107568, Sep 12, 2006
Filed:
Oct 7, 2002
Appl. No.:
10/266719
Inventors:
Darren C. Cronquist - San Francisco CA, US
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 18, 716 3, 717146
Abstract:
One embodiment of the invention is a method for producing a hardware solver for intermediate code comprising analyzing intermediate code for at least one instantiation that may cause at least one of wire delay and congestion in the solver, forming compensation for the at least one instantiation, and forming the solver in accordance with the compensation.

Reconfigurable Computing Architecture For Providing Pipelined Data Paths

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US Patent:
60237422, Feb 8, 2000
Filed:
Jul 18, 1997
Appl. No.:
8/897094
Inventors:
William Henry Carl Ebeling - Seattle WA
Darren Charles Cronquist - Seattle WA
Paul David Franklin - Seattle WA
Assignee:
University of Washington - Seattle WA
International Classification:
G06F 1314
US Classification:
710107
Abstract:
A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and instructions are referred to as dynamic control. A reconfigurable data path (12) has a plurality of elements including functional units (32, 36), registers (30), and memories (34) whose interconnection and functionality is determined by a combination of static and dynamic control. These elements are connected together, using the static configuration, into a pipelined data path that performs a computation of interest. The dynamic control signals (21) are suitably used to change the operation of a functional unit and the routing of signals between functional units. The static control signals (23) are provided each by a static memory cell (62) that is written by a host (13). The controller (14) generates control instructions (16) that are interpreted by a control path (18) that computes the dynamic control signals.

Latency Offset In Pre-Clock Tree Synthesis Modeling

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US Patent:
20220180031, Jun 9, 2022
Filed:
Dec 8, 2021
Appl. No.:
17/643359
Inventors:
- Mountain View CA, US
Paul Eugene Richard LIPPENS - Eindhoven, NL
Darren Charles CRONQUIST - San Francisco CA, US
International Classification:
G06F 30/32
G06F 111/04
Abstract:
Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Providing Guidance To An Equivalence Checker When A Design Contains Retimed Registers

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US Patent:
20200026813, Jan 23, 2020
Filed:
Jul 17, 2018
Appl. No.:
16/037936
Inventors:
- Mountain View CA, US
Darren Charles Cronquist - San Francisco CA, US
Peter Wilhelm Joseph Zepter - Mountain View CA, US
Navneet Kakkar - Bangalore, IN
Sridhar Keladi - Bangalore, IN
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
Abstract:
Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.
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Darren C Cronquist from San Francisco, CA, age ~53 Get Report