David S Doman

8598633, Dec 3, 2013

Jan 16, 2012

13/351101

Marc Tarabbia - Pleasant Valley NY, US
James B. Gullette - Dresden, DE
Mahbub Rashed - Santa Clara CA, US
David S. Doman - Austin TX, US
Irene Y. Lin - Los Altos Hills CA, US
Ingolf Lorenz - Ottendorf-Okrilla, DE
Larry Ho - Cupertino CA, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Jongwook Kye - Pleasanton CA, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Jason E. Stephens - Beacon NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 23/52

257207, 257211

A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

8618607, Dec 31, 2013

Jul 2, 2012

13/539830

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/02

257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

20130099856, Apr 25, 2013

Oct 24, 2011

13/279608

David S. Doman - Austin TX, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 27/105

327566

Disclosed herein are various methods and circuits for achieving rational fractional drive strengths in circuits employing FinFET devices. In one example, the device disclosed herein includes a semiconducting substrate, a first plurality of FinFET transistors formed in and above the substrate, wherein each of the first plurality of FinFET transistors is adapted to produce an individual drive current, and wherein the first plurality of FinFET transistors are configured in a series circuit. The drive current resulting from the series circuit is a rational fraction of the individual drive current.

20130100590, Apr 25, 2013

Oct 24, 2011

13/279687

David S. Doman - Austin TX, US

GLOBALFOUNDRIES INC. - Grand Cayman

H05K 7/00

36167901

Disclosed herein are integrated circuit devices having stacked power supplies and methods of making such integrated circuit devices. In one example, the device includes a first power supply structure, a second power supply structure electrically isolated from the first power supply structure, wherein at least a portion of the second power supply structure is positioned vertically below at least a portion of the first power supply structure, wherein the first power supply structure is one of an interruptible or an uninterruptible power supply structure, while the second power supply structure is the other of the interruptible or the uninterruptible power supply structure, a plurality of constant-power circuits conductively coupled to whichever of the first or second power supply structure that is the uninterruptible power supply and a plurality of interruptible-power circuits conductively coupled to whichever of the first or second power supply structure that is the interruptible power supply.

20130275935, Oct 17, 2013

Apr 13, 2012

13/446418

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Dinesh Somasekhar - Portland OR, US
Yan Wang - San Jose CA, US
Yunfei Deng - Sunnyvale CA, US
Navneet Jain - Milpitas CA, US
Jongwook Kye - Pleasanton CA, US
Ali Keshavarzi - Cupertino CA, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 17/50

716113

An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

20130280905, Oct 24, 2013

Apr 24, 2012

13/454928

David S. Doman - Austin TX, US
Mahbub Rashed - Santa Clara CA, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/768
G06F 17/50

438618, 716127, 257E21575

A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

20140027918, Jan 30, 2014

Jul 30, 2012

13/561932

Mahbub Rashed - Santa Clara CA, US
Marc Tarabbia - Pleasant Valley NY, US
Chinh Nguyen - Austin TX, US
David Doman - Austin TX, US
Juhan Kim - Santa Clara CA, US
Xiang Qi - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 23/535
H01L 21/768

257773, 438599, 257E2159, 257E23168

An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

20180182674, Jun 28, 2018

Feb 26, 2018

15/905621

- Grand Cayman, KY
Tuhin Guha Neogi - Fishkill NY, US
Scott Luning - Albany NY, US
David Doman - Austin TX, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/8234
H01L 29/66
H01L 29/08
H01L 23/528
H01L 23/522
H01L 21/768
H01L 21/027
H01L 21/321
H01L 21/311

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.