David Lyle Matheny

6360189, Mar 19, 2002

Aug 31, 1998

09/144264

Christopher Neal Hinds - Austin TX
David Vivian Jaggar - Austin TX
David Terrence Matheny - Austin TX

ARM Limited - Cambridge

G06F 738

703 2, 708501, 708523

A data processing apparatus and method is provided for performing a multiply-accumulate operation A+(B*C) in response to a single instruction identifying said multiply-accumulate operation. The data processing operation comprises a multiplier for multiplying values B and C to generate an unrounded multiplication result, the multiplier further being arranged to generate first data required for rounding determination, and an adder for adding the unrounded multiplication result to a value A to generate an unrounded multiply-accumulate result, the adder further being arranged to generate second data required for rounding determination. Determination logic is then provided for using the first and second data to determine one or more rounding values required to produce a final multiply-accumulate result equivalent to the execution of a separate multiply instruction incorporating rounding, followed by a separate add instruction incorporating rounding. Rounding logic is then arranged to apply the one or more rounding values to generate the final multiply-accumulate result. By this approach, dedicated multiply-accumulate logic can be provided to enable fast execution of a multiply-accumulate instruction, whilst producing a result which is compliant with the IEEE 754-1985 standard.

7240144, Jul 3, 2007

Apr 2, 2004

10/815961

Tan Ba Tran - Round Rock TX, US
Gerard Richard Williams - Sunset Valley TX, US
David Terrence Matheny - Austin TX, US
David Walter Flynn - Cambridge, GB

Arm Limited - Cambridge

G06F 12/00

711 5, 711105, 712215

A data processor core comprising: a memory access interface portion operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core; a data processing portion operable to perform data processing operations; a read/write port operable to transfer data from said processor core to at least two buses A, B said at least two buses being operable to provide data communication between said processor core and said at least one memory , said at least one memory comprising at least two portions A, B, each of said at least two buses A, B being operable to provide data access to respective ones of said at least two portions A, B; arbitration logic associated with said read/write port ; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

7380095, May 27, 2008

Jun 30, 2004

10/882483

David L. Matheny - Cedar Park TX, US

Intel Corporation - Santa Clara CA

G06F 12/08

711202, 711 2, 711207

In some embodiments, the invention involves a system and method relating to switching to protected mode to access extended memory while executing instruction code that is designed for real mode memory access. In at least one embodiment, the present invention is intended to enable complex option-ROM code to be executed during pre-boot without corrupting system memory used by the BIOS or other option-ROMs. Other embodiments are described and claimed.

7552319, Jun 23, 2009

Jun 30, 2004

10/880830

David Matheny - Cedar Park TX, US

Intel Corporation - Santa Clara CA

G06F 15/177

713 1, 713 2, 711165, 711202, 711206

An example method involves detecting a memory relocation process and disabling memory access to a memory block in response to detecting the memory relocation process. The example method also involves determining an absolute address value associated with the memory block and storing the absolute address value.

20020161883, Oct 31, 2002

Apr 30, 2001

09/846521

David Matheny - South Jordan UT, US
Dale Taylor - Lindon UT, US
Richard Winterton - Provo UT, US

G06F015/173

709/224000, 709/223000

In an embodiment, a network management system is capable of performing a coordinated discovery operation on devices in a network using a number of discovery and aggregator agents. Data collected and generated by the agents may be coalesced into a database file. New agents may be added to the system as plug-ins by registering an XML file with a network manager.

20050216715, Sep 29, 2005

Mar 29, 2004

10/811533

David Matheny - Cedar Park TX, US
Eric Blair - Austin TX, US

G06F009/00

713001000

A method includes receiving input from a user and, in response to the input, selecting one of a BCV (boot connection vector) pointer and a BEV (bootstrap entry vector) pointer to have a non-null value.

20050251676, Nov 10, 2005

May 5, 2004

10/839816

Hemal Shah - Austin TX, US
David Matheny - Cedar Park TX, US
Jeff Zachem - Austin TX, US

Intel Corporation - Santa Clara CA

H04L009/00

713160000

A card receives data encoded in a protocol. The data may be divided into packets, or still in a protocol data unit. If still in a protocol data unit, the card divides the data into packets of appropriate size. Digests appropriate to the protocol are computed and inserted into the packets. Checksums are generated for the packets that need them, such as the packet now including the digest. The packets may then be transmitted to a recipient.

20050289288, Dec 29, 2005

Jun 25, 2004

10/877763

David Matheny - Cedar Park TX, US
Navneet Malpani - Austin TX, US

G06F012/00

711102000, 713002000, 711154000

The inventive subject matter provides systems, methods, data structures, and software to compress and decompress a memory image such as an expansion read-only memory (ROM). Some embodiments include attaching a compressed memory image to a decompression shell to create a data structure that includes decompression instructions. Other embodiments include loading a memory image from a data structure by decompressing the memory image according to decompression instructions included in the data structure.