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Ilya V Karpov

from Portland, OR
Age ~60

Ilya Karpov Phones & Addresses

  • 3969 NW Brookview Way, Portland, OR 97229 (408) 806-0999
  • Fairview, OR
  • Copperopolis, CA
  • Tavernier, FL
  • Homestead, FL
  • Welches, OR
  • Fremont, CA
  • Santa Clara, CA

Resumes

Resumes

Ilya Karpov Photo 1

Engineer At Intel Corporation

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Position:
Engineer at Intel Corporation, Components Research
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Intel Corporation, Components Research - Portland, OR since Oct 2011
Engineer

Intel, California Technology and Manufacturing Jan 2002 - Oct 2011
Engineer

Intel Corporation Dec 1999 - Jan 2002
Engineer

Mitsubishi Silicon America Jan 1997 - Dec 1999
Sr. Product Development Engineer, Research and Development Group

Harris Semiconductor Apr 1996 - Sep 1996
Intern
Education:
Stanford University 2007 - 2008
Stanford Certified Advanced Project Manager, Project Management
University of Minnesota-Twin Cities 1991 - 1996
Ph.D., Materials Science and Engineering
National University of Science and Technology "MISIS"  (Moscow Institute of Steel and Alloys) 1982 - 1986
MS, Physics of Semiconductor Materials and Devices
Honor & Awards:
Senior Member, IEEE Stanford Certified Advanced Project Manager
Languages:
Russian
Ilya Karpov Photo 2

Ilya Karpov

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Ilya Karpov
Managing
IK INVESTMENTS LLC
4775 Collins Ave APT 705, Miami Beach, FL 33140
98-30 SW 77 Ave STE 125, Miami, FL 33156
9830 SW 77 Ave, Miami, FL 33156
98-30 SW 77 Ave - STE 125, Miami, FL 33156

Publications

Us Patents

Ferroelectric Memory-Based Synapses

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US Patent:
20200194049, Jun 18, 2020
Filed:
Dec 14, 2018
Appl. No.:
16/221175
Inventors:
- Santa Clara CA, US
Ilya Karpov - Portland OR, US
Ian Young - Portland OR, US
International Classification:
G11C 11/22
H01L 27/1159
G11C 11/54
G06N 3/02
Abstract:
An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.

Backend Electrostatic Discharge Diode Apparatus And Method Of Fabricating The Same

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US Patent:
20190304963, Oct 3, 2019
Filed:
Mar 29, 2018
Appl. No.:
15/940899
Inventors:
- Santa Clara CA, US
Ilya Karpov - Portland OR, US
Brian Doyle - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Abhishek Sharma - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 27/02
H01L 29/861
Abstract:
A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.
Ilya V Karpov from Portland, OR, age ~60 Get Report