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Erik Witmer Egan

from Portland, OR
Age ~63

Erik Egan Phones & Addresses

  • 3060 NW Cornell Rd, Portland, OR 97210 (510) 290-1085
  • Lahaina, HI
  • 5437 Lawton Ave, Oakland, CA 94618 (510) 652-7103
  • Piedmont, CA
  • 36 Highgate Rd, Berkeley, CA 94707
  • Kensington, CA
  • 1811 Alta Vista Ave, Austin, TX 78704
  • Phoenix, AZ
  • Seattle, WA
  • Champaign, IL
  • Alameda, CA
  • 5437 Lawton Ave, Oakland, CA 94618 (562) 244-8021

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

Business Records

Name / Title
Company / Classification
Phones & Addresses
Erik Egan
Owner
Proto to Product Consulting
Business Consulting Services
5437 Lawton Ave, Oakland, CA 94618
(510) 652-7103

Publications

Us Patents

Compact, Low Insertion Loss, High Yield Arrayed Waveguide Grating

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US Patent:
6697553, Feb 24, 2004
Filed:
Feb 15, 2002
Appl. No.:
10/077581
Inventors:
Jyoti Kiron Bhardwaj - Cupertino CA
Robert James Brainard - Sunnyvale CA
David J. Chapman - San Jose CA
Douglas E. Crafts - San Jose CA
David Dougherty - Sunnyvale CA
Erik W. Egan - Oakland CA
James F. Farrell - San Jose CA
Mark B. Farrelly - San Jose CA
Niranjan Gopinathan - Santa Clara CA
Kenzo Ishida - Saratoga CA
David K. Nakamoto - Sunnyvale CA
Thomas Thuan Nguyen - San Jose CA
Suresh Ramalingam - Fremont CA
Steven M. Swain - San Jose CA
Sanjay M. Thekdi - Santa Clara CA
Anantharaman Vaidyanathan - San Jose CA
Hiroaki Yamada - San Jose CA
Yingchao Yan - Milpitas CA
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
G02B 634
US Classification:
385 37, 385 24, 385 46, 385 43
Abstract:
A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e. g. , width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Waveguide Stress Engineering And Compatible Passivation In Planar Lightwave Circuits

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US Patent:
6947653, Sep 20, 2005
Filed:
Oct 12, 2001
Appl. No.:
09/977065
Inventors:
Jyoti Kiron Bhardwaj - Cupertino CA, US
Robert James Brainard - Sunnyvale CA, US
David Dougherty - Sunnyvale CA, US
Erik W. Egan - Oakland CA, US
Niranjan Gopinathan - Santa Clara CA, US
David K. Nakamoto - Sunnyvale CA, US
Thomas Thuan Nguyen - San Jose CA, US
Sanjay M. Thekdi - Santa Clara CA, US
Anantharaman Vaidyanathan - San Jose CA, US
Hiroaki Yamada - San Jose CA, US
Yingchao Yan - Milpitas CA, US
Assignee:
JDS Uniphase Corporation - San Jose CA
International Classification:
G02B006/10
G02B006/13
G02F001/295
US Classification:
385129, 385 10, 385 11, 385132, 438 31
Abstract:
A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

Nanoembossed Shapes And Fabrication Methods Of Wire Grid Polarizers

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US Patent:
20100134719, Jun 3, 2010
Filed:
Jul 24, 2008
Appl. No.:
12/733037
Inventors:
Chad Johns - San Leandro CA, US
Erik Egan - Oakland CA, US
Michael J. Little - Garden Valley CA, US
International Classification:
G02F 1/1335
G02B 5/30
B05D 5/06
US Classification:
349 62, 359486, 427162
Abstract:
A wire grid polarizer may be formed by embossing a substrate surface with a mold having a plurality of grooves to form raised ridges; and depositing a metal line profile onto the ridges through one or more baffles oriented at an oblique angle to the normal of the substrate. The metal line profile is characterized by a cross-sectional width that tapers such that the metal line profile is wider proximate a vertex of the ridges than proximate a base of the ridges. A wire grid polarizer may comprise a substrate with a plurality of raised ridges and a plurality of metal lines on the raised ridges. The metal lines are characterized by cross-sectional metal line profiles having triangular shapes with a tip down configuration. Such a wire grid polarizer may be used in a liquid crystal display.
Erik Witmer Egan from Portland, OR, age ~63 Get Report