Fred O Barthold from 1873 Wilstone Ave, Encinitas, CA 92024, age 89

Dc-Dc Converter

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US Patent:

7777458, Aug 17, 2010

Filed:

Nov 14, 2008

Appl. No.:

12/291993

Inventors:

Fred O. Barthold - San Diego CA, US

International Classification:

G05F 1/613

US Classification:

323224, 323232, 323272

Abstract:

A Single Ended Primary Inductance Converter (SEPIC) fed BUCK converter includes: a first switch configured to open or close according to a first signal; a SEPIC portion coupled to the first switch and coupled to an energy source, the SEPIC portion comprising a first set of one or more passive components; a BUCK converter portion coupled to the first switch, the BUCK converter portion comprising a second set of one or more passive components. While the first switch is closed, the SEPIC portion is configured to store energy from an energy source in at least some of the first set of passive components and deliver energy to the BUCK portion, and the BUCK converter portion is configured to deliver energy to a load and to store energy in at least some of the second set of passive components. While the first switch is open, the SEPIC portion is configured to deliver at least some of its stored energy to the load, and the BUCK converter portion is configured to deliver at least some of its stored energy to the load.

Sepic Fed Buck Converter

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US Patent:

7812577, Oct 12, 2010

Filed:

Nov 14, 2008

Appl. No.:

12/291992

Inventors:

Fred O. Barthold - San Diego CA, US

International Classification:

G05F 1/656
G05F 1/652

US Classification:

323222, 323224, 323282, 323284, 323288, 323290

Abstract:

A Single Ended Primary Inductance Converter (SEPIC) fed BUCK converter includes: a first switch configured to open or close according to a first signal; a SEPIC portion coupled to the first switch and coupled to an energy source, the SEPIC portion comprising a first set of one or more passive components; a BUCK converter portion coupled to the first switch, the BUCK converter portion comprising a second set of one or more passive components. While the first switch is closed, the SEPIC portion is configured to store energy from an energy source in at least some of the first set of passive components and deliver energy to the BUCK portion, and the BUCK converter portion is configured to deliver energy to a load and to store energy in at least some of the second set of passive components. While the first switch is open, the SEPIC portion is configured to deliver at least some of its stored energy to the load, and the BUCK converter portion is configured to deliver at least some of its stored energy to the load.

Full Wave Buck-Boost Power Converter With Buck Power Converter Properties

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US Patent:

54368189, Jul 25, 1995

Filed:

Feb 14, 1994

Appl. No.:

8/196398

Inventors:

Fred O. Barthold - Leucadia CA

International Classification:

H02M 3335

US Classification:

363 21

Abstract:

A continuous mode full wave power converter topology which integrates the buck-boost (flyback) and buck converter properties. The voltage transfer function is M=(D/(1-D)), characteristic of the buck-boost (flyback) converter. Characteristic of the full wave buck converter, the inductor current is source continuous during the alternate D intervals, source discontinuous during the simultaneous (1-D) intervals, and load continuous during both the D and (1-D) intervals.

Source Volt-Ampere/Load Volt-Ampere Differential Converter

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US Patent:

47348399, Mar 29, 1988

Filed:

Mar 23, 1987

Appl. No.:

7/028900

Inventors:

Fred O. Barthold - Leucadia CA

International Classification:

H02M 3335

US Classification:

363 16

Abstract:

A source V-A/load V-A differential converter (single quaddrant DC-DC topology) combines the canonical functions of both the boost and buck converter topologies. Basic advantages of the boost and buck topologies are retained, disadvantages of these and prior art compound topologies are eliminated, and several entirely new and useful functions are realized. These new functions include sub-microsecond source voltage/load step response (independent of feedback loop parameters), extremely wide source voltage range, very high conversion efficiency/power density, multiple auxiliary outputs with closely held voltage range parameters (without resort to minimum load, pre-load, or sub-regulation), galvanic input/output isolation, enhanced capacitance safety/energy storage, reduced gain bandwidth requirements, and intrinsic stability. The differential term derives from the transfer function for this new compound topology, i. e. , x=. delta. (a+x).

Power Transistor Switch

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US Patent:

40428443, Aug 16, 1977

Filed:

Apr 19, 1976

Appl. No.:

5/678239

Inventors:

Fred O. Barthold - Leucadia CA

International Classification:

H03K 345

US Classification:

307314

Abstract:

A power transistor switch for switching high-amperage, direct-current through a low forward impedance, consisting of a transformer which couples a control pulse through separate multifilar secondary windings to each base element of a plurality of transistors. The utilization of multiple junction transistor geometry results in a rapid transition, i. e. , low transition time consistent with a low forward impedance and cost savings because of the inherent economies in multiple junction transistors, without resort to individual discrete emitter or base resistances with the power loss inherent in their use.

Planar Core With High Magnetic Volume Utilization

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US Patent:

20160111209, Apr 21, 2016

Filed:

Dec 21, 2015

Appl. No.:

14/977568

Inventors:

Fred O. Barthold - Leucadia CA, US

International Classification:

H01F 41/02

Abstract:

A disclosed method comprises: specifying a WAproduct of a first transformer having a three-legged core; determining a window area Wof the first transformer; determining parameters of the first transformer, including a core area A, a height of c, and a width of b; specifying, based at least in part on the parameters of the first transformer, a second transformer having the WAproduct, the window area W, and the core area Aand comprising: a first magnetic portion comprising: a first plurality of leg posts that is to be surrounded by a first set of windings; and a first plurality of center portions that is not to be surrounded by windings; and a second magnetic core portion comprising: a second plurality of leg posts that is to be surrounded by a second set of windings; and a second plurality of center portions that do not receive windings.

Harmonic Displacement Reduction

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US Patent:

20150194874, Jul 9, 2015

Filed:

Oct 29, 2014

Appl. No.:

14/527309

Inventors:

Fred O. Barthold - Leucadia CA, US

International Classification:

H02M 1/32
H02M 1/12

Abstract:

Reducing voltage excursions in a circuit comprises: performing resonant commutation, including transferring, via a first set of one or more diodes, energy stored by a set of one or more parasitic inductances to a set of one or more capacitors; and performing recovery-to-load, including discharging energy stored in the set of one or more capacitors via a second set of one or more diodes, through the set of one or more parasitic inductances to a load of the circuit.

Planar Core With High Magnetic Volume Utilization

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US Patent:

20140340188, Nov 20, 2014

Filed:

Apr 7, 2014

Appl. No.:

14/247000

Inventors:

Fred O. Barthold - Leucadia CA, US

International Classification:

H01F 27/24
H01F 41/04
H01F 41/02

US Classification:

336214, 29607, 29606

Abstract:

A structure is disclosed, comprising: a first magnetic core portion comprising: a first plurality of leg posts that are to be surrounded by a first set of windings; and a first plurality of center portions that are not to be surrounded by windings; and a second magnetic core portion comprising: a second plurality of leg posts that are to be surrounded by a second set of windings; and a second plurality of center portions that are not to be surrounded by the second set of windings, wherein the first set of center portions and the second set of center portions are configured to provide a plurality of physically separate magnetic flux paths.