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Gautam B Doshi

from Cupertino, CA
Age ~59
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Also known as:
Gautam B Doski, Gavtam Doshi
Related to:
Jagruti Shah, 45Arpan Shah, 40Ankit Shah, 42Divya ShahRomin Shah, 38
Connected to:
Ashwini A Doshi, 41Bijel K Doshi, 41Birva Doshi, 42Pragalbha M Doshi, 47Pushpa B Doshi, 82Rajendra P Doshi, 62Sanjana C DoshiShilpa Y Doshi, 65Shreya P Doshi, 38Siddhi Doshi, 31

Gautam Doshi Phones & Addresses

  • Cupertino, CA
  • 1021 Riverside Dr, San Jose, CA 95129 (408) 517-1107
  • 3819 Hancock Dr, Santa Clara, CA 95051 (408) 248-7224 (408) 248-7227 (408) 296-0491
  • Sunnyvale, CA
  • 1021 W Riverside Way, San Jose, CA 95129

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Graduate or professional degree

Resumes

Resumes

Gautam Doshi Photo 1

Gautam Doshi

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Location:
20192 Joseph Cir, Cupertino, CA 95014
Industry:
Semiconductors
Work:
Intel Corporation Apr 2014 - Nov 2017
Senior Principal Engineer
Education:
University of California, Berkeley 1986 - 1988
Masters, Master of Engineering, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science, Engineering Indian Institute of Technology, Bombay 1982 - 1986
Bachelors, Bachelor of Technology, Electronics Engineering, Electronics
Skills:
Semiconductors
Asic
Processors
Soc
Vlsi
Computer Architecture
Integrated Circuit Design
Debugging
Hardware Architecture
Microprocessors
Rtl Design
Application Specific Integrated Circuits
System on A Chip
Languages:
English
Gautam Doshi Photo 2

Gautam Doshi

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Gautam Doshi
Secretary
FINE-LINE CIRCUITS LIMITED WHICH WILL DO BUSINESS IN CALIFORNIA AS FINE LINE PRINTED CIRCUITS
Manufacturer of Printed Circuit Boards
4320 Stevens Crk Blvd SUITE # 271, San Jose, CA 95129
(408) 244-6149

Publications

Us Patents

Processor Architecture Having Two Or More Floating-Point Status Fields

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US Patent:
6370639, Apr 9, 2002
Filed:
Oct 10, 1998
Appl. No.:
09/169482
Inventors:
Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA
Guillermo Juan Rozas - Los Gatos CA
Assignee:
Institute for the Development of Emerging Architectures L.L.C. - Cupertino CA
International Classification:
G06F 9312
US Classification:
712222, 712224, 712228, 712235, 712239
Abstract:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Method And Apparatus For Managing Temporal And Non-Temporal Data In A Single Cache Structure

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US Patent:
6542966, Apr 1, 2003
Filed:
Jul 16, 1998
Appl. No.:
09/118204
Inventors:
John Crawford - Santa Clara CA
Gautam Doshi - Sunnyvale CA
Stuart E. Sailer - Campbell CA
John Wai Cheong Fu - Saratoga CA
Gregory S. Mathews - Santa Clara CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1212
US Classification:
711133
Abstract:
A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

Methods And Apparatus For Controlling Exponent Range In Floating-Point Calculations

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US Patent:
6578059, Jun 10, 2003
Filed:
Oct 10, 1998
Appl. No.:
09/169669
Inventors:
Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA
Assignee:
Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA
International Classification:
G06F 748
US Classification:
708496, 712222
Abstract:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Mechanism For Software Pipelining Loop Nests

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US Patent:
6820250, Nov 16, 2004
Filed:
May 9, 2002
Appl. No.:
10/143163
Inventors:
Kalyan Muthukumar - Cupertino CA
Gautam B. Doshi - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 944
US Classification:
717116, 717150
Abstract:
A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.

Reduced-Hardware Soft Error Detection

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US Patent:
7035891, Apr 25, 2006
Filed:
Aug 27, 2002
Appl. No.:
10/228432
Inventors:
Sivakumar Makineni - Sunnyvale CA, US
Gautam B. Doshi - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/16
US Classification:
708530, 708534
Abstract:
A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.

System And Method For Software-Pipelining Of Loops With Sparse Matrix Routines

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US Patent:
7263692, Aug 28, 2007
Filed:
Jun 30, 2003
Appl. No.:
10/612724
Inventors:
Kalyan Muthukumar - Bangalore, IN
Gautam Doshi - Santa Clara CA, US
Dattatraya Kulkarni - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717150, 717157, 717160
Abstract:
A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.

Computer Product And Method For Sparse Matrices

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US Patent:
20020161812, Oct 31, 2002
Filed:
Nov 7, 2001
Appl. No.:
10/055406
Inventors:
Gautam Doshi - Sunnyvale CA, US
Roger Golliver - Beaverton OR, US
Bob Norin - Tigard OR, US
International Classification:
G06F007/52
US Classification:
708/607000
Abstract:
A computer program product and method for multiplying a sparse matrix by a vector are disclosed. The computer program product includes a computer readable medium for storing instructions, which, when executed by a computer, cause the computer to efficiently multiply a sparse matrix by a vector, and produce a resulting vector. The computer is made to create a first array containing the non-zero elements of the sparse matrix, and a second array containing the end_of_row position of the last non-zero element in each row of the sparse matrix. A variable is initialized, and then, for each row of the second array, the computer is made to do one of two things. Either, it equates the variable to the sum of the variable and the product of a particular element of the first array and a particular element of the vector. Or, it equates a particular element of the resulting vector to the variable, and then equates the variable to a particular value.

Dependence Compensation For Sparse Computations

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US Patent:
20040123280, Jun 24, 2004
Filed:
Dec 19, 2002
Appl. No.:
10/325169
Inventors:
Gautam Doshi - Santa Clara CA, US
Dattatraya Kulkarni - Santa Clara CA, US
Anthony Roide - Phoenix AZ, US
Antonio Valles - Gilbert AZ, US
International Classification:
G06F009/45
US Classification:
717/161000, 717/150000
Abstract:
An embodiment of a compiler technique for decreasing sparse matrix computation runtime parallelizes loads from adjacent iterations of unrolled loop code. A dependence check code is statically inserted to identify dependence between store and load dynamically, and information is passed to a code scheduler for scheduling independent parallel computation and potentially dependent computations at suitable latencies.
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Gautam B Doshi from Cupertino, CA, age ~59 Get Report