Search

George Stojakovic

from Hopewell, NY
Get Report
Related to:
Elke Stojakovic, 55Djordje B Stojakovic, 67
Connected to:
Erin K Stojakovic, 47Rade Stojakovic, 69Djordje Stojanovic, 76Katerina StojanovaTamara Stojanovski, 57Vladan Stojanovic, 43John A Stojevich, 92Heidi A Stojic, 61Biljana Stojkovska, 51Dagmar M Stojkovic, 67

George Stojakovic Phones & Addresses

  • Hopewell, NY
  • 78 Star Mill Rd, Fishkill, NY 12524 (845) 897-3077
  • Poughkeepsie, NY
  • 100 Woodcrest Dr, Hopewell Jct, NY 12533

Work

Position: Manager

Resumes

Resumes

George Stojakovic Photo 1

Manager

View page
Work:

Manager

Publications

Us Patents

Material Combinations For Tunnel Junction Cap Layer, Tunnel Junction Hard Mask And Tunnel Junction Stack Seed Layer In Mram Processing

View page
US Patent:
6815248, Nov 9, 2004
Filed:
Apr 18, 2002
Appl. No.:
10/124950
Inventors:
Rainer Leuschner - Mohegan Lake NY
George Stojakovic - Hopewell Junction NY
Xian J. Ning - Mohegan Lake NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 2100
US Classification:
438 59, 438 3, 438 48, 438396, 438244, 438250, 438253, 438239, 257 71, 257252, 257295, 257298, 257303, 257414
Abstract:
A resistive memory device ( ) and method of manufacturing thereof comprising a cap layer ( ) and hard mask layer ( ) disposed over magnetic stacks ( ), wherein either the cap layer ( ) or hard mask layer ( ) comprise WN. A seed layer ( ) disposed beneath the magnetic stacks ( ) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.

Tungsten Hard Mask

View page
US Patent:
6815364, Nov 9, 2004
Filed:
Sep 28, 2001
Appl. No.:
09/967795
Inventors:
George Stojakovic - Hopewell Junction NY
Matthias Lipinski - Wappingers Falls NY
Assignee:
Infineon Technologies North America Corp. - San Jose CA
International Classification:
H01L 21302
US Classification:
438710, 438714, 438717, 438720, 438725, 438742
Abstract:
Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said pattern with a plasma etch that is selective for said metal-based surface with respect to tungsten, and executing a flash etch selective for tungsten, said etch of at least a minimum duration effective in removing substantially all defects caused by tungsten particulate contaminating said wafer. In another aspect of the first embodiment, said tungsten-based hard mask comprises a material selected from tungsten or an alloy thereof. In another aspect of the first embodiment, said metal based surface comprises a material selected from aluminum or an alloy thereof.

Fabrication Process For A Magnetic Tunnel Junction Device

View page
US Patent:
6984529, Jan 10, 2006
Filed:
Sep 10, 2003
Appl. No.:
10/659136
Inventors:
George Stojakovic - Hopewell Junction NY, US
Rajiv M. Ranade - Brewster NY, US
Ihar Kasko - Fishkill NY, US
Joachim Neutzel - Fishkill NY, US
Keith R. Milkove - Beacon NY, US
Russell D. Allen - Mahopac NY, US
Kim Poong Mee Lee, legal representative - Hartsdale NY, US
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/027
US Classification:
438 3
Abstract:
A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Methods And Apparatus For The Optimization Of Etch Resistance In A Plasma Processing System

View page
US Patent:
7316785, Jan 8, 2008
Filed:
Jun 30, 2004
Appl. No.:
10/883282
Inventors:
Yoko Yamaguchi Adams - Fremont CA, US
George Stojakovic - Fishkill NY, US
Alan Miller - Moraga CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
C03C 25/68
US Classification:
216 67, 216 51, 216 72, 216 79, 216 80, 216104, 438710, 438723, 438724, 438743, 438744
Abstract:
In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

Patterning Metal Stack Layers Of Magnetic Switching Device, Utilizing A Bilayer Metal Hardmask

View page
US Patent:
20040084400, May 6, 2004
Filed:
Oct 30, 2002
Appl. No.:
10/283348
Inventors:
Gregory Costrini - Hopewell Junction NY, US
John Hummel - Millbrook NY, US
George Stojakovic - Hopewell Junction NY, US
International Classification:
B44C001/22
US Classification:
216/022000
Abstract:
Patterning metal stack layers of a magnetic switching device to enable a critical lithography level to be made on planar substrate without any topography and enable a second lithography step without topography from a top patterned hardmask, comprising: a) depositing a magnetic tunnel junction stack over oxide layer containing metal transistors surrounded by Cu lines, in which a via connects pinned magnet to at least one metal transistor, forming a bilayer hardmask by depositing layer of TiN on magnetic tunnel junction stack and a layer of W on TiN; b) patterning a junction of the device by opening a portion of W hardmask over metal transistor with an etch stop on TiN hardmask, depositing a tunnel junction resist and developing a resist feature on top of hardmask; c) opening the remaining W hardmask and stripping remaining resist and etch residue; d) performing a metal etch to isolate one device from an adjacent device and depositing anti-reflective coating; e) transferring resist pattern into the TiN hardmask by opening the TiN hardmask and stripping any remaining resist and etch residue; f) patterning to isolate one device from an adjacent device to form a memory array by etching a portion of the top layer of the magnetic tunnel junction stack and opening the remaining portion of the TiN hardmask selective to the W hardmask that holds pattern for the device junction; and g) affecting junction pattern transfer using the W hardmask by performing a tunnel junction etch and capping the magnetic switching device by depositing Al and oxidizing the deposited aluminum to form a layer of AlOto getter corrosive residuals and passivate metal surface of device from oxidation and/or corrosion.

System And Method For Performing A Metal Layer Rie Process

View page
US Patent:
20040203242, Oct 14, 2004
Filed:
Apr 11, 2003
Appl. No.:
10/411279
Inventors:
George Stojakovic - Hopewell Junction NY, US
Matthias Lipinski - Dresden, DE
International Classification:
H01L021/302
H01L021/461
US Classification:
438/690000
Abstract:
A method and a system for performing a metal reactive ion etching (RIE) process is disclosed. The metal RIE process comprises at least three steps: a metal RIE step, a stripping step and a wet cleaning step. The metal RIE step and the stripping step are carried out in a main reactive chamber.

Fence-Free Etching Of Iridium Barrier Having A Steep Taper Angle

View page
US Patent:
20050045937, Mar 3, 2005
Filed:
Sep 3, 2003
Appl. No.:
10/654376
Inventors:
Ulrich Egger - Kanagawa-ken, JP
Haoren Zhuang - Tokyo-to, JP
George Stojakovic - Hopewell Junction NY, US
Kazuhiro Tomioka - Kanagawa-ken, JP
Assignee:
Infineon Technologies AG - Munich
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
H01L021/00
H01L021/8242
H01L029/76
H01L031/119
H01L027/108
US Classification:
257306000, 438003000, 438250000, 257310000
Abstract:
An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Dry Process For Cleaning Residues/Polymers After Metal Etch

View page
US Patent:
6184134, Feb 6, 2001
Filed:
Feb 18, 2000
Appl. No.:
9/506892
Inventors:
Nirmal Chaudhary - Wappingers Falls NY
Xian J. Ning - Mohegan Lake NY
George Stojakovic - Poughkeepsie NY
Assignee:
Infineon Technologies North America Corp. - San Jose CA
International Classification:
H01L 2144
US Classification:
438669
Abstract:
An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO. sub. 3 strip at low temperature to remove additional residue; and rinsing the SO. sub. 3 stripped material with de-ionized water to remove any remaining resist and residue.
Control profile
George Stojakovic from Hopewell, NY Get Report