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Hassan K Bazargan

from Morgan Hill, CA
Age ~66
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Also known as:
Hassan Kazemzadeh Bazargan, Hassan N
Phone and address:
2845 Hay Loft Way, Morgan Hill, CA 95037
(408) 725-8494
Related to:
Bijan BazarganCamellia BazarganMojgan Sefidpour, 60Mahvash S Nabipour, 64Shahram Nabipour, 54Gissou Bazargan, 58Reza Nabipour, 94
Connected to:
Bryan Bazarte, 51William C Bazata, 61Kristina M Bazavilvazo, 48Chuck BazeGinger L Baze, 75Genelle D Bazel, 58Matthew J Bazel, 56Timothy J Bazell, 62Daniela A Bazemore, 62Diana Bazemore

Hassan Bazargan Phones & Addresses

  • 2845 Hay Loft Way, Morgan Hill, CA 95037 (408) 725-8494
  • 12200 Miller Ave, Saratoga, CA 95070 (408) 725-8494
  • Sunnyvale, CA
  • 1299 Starglo Pl, San Jose, CA 95131
  • Baton Rouge, LA

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Publications

Us Patents

Method And Circuit For Hot Swap Protection

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US Patent:
6810458, Oct 26, 2004
Filed:
Mar 1, 2002
Appl. No.:
10/090257
Inventors:
Hassan K. Bazargan - San Jose CA
Jian Tan - Milpitas CA
Atul V. Ghia - San Jose CA
Suresh M. Menon - Sunnyvale CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1300
US Classification:
710302, 710301, 326 87
Abstract:
A hot swap protection circuit ( ) for an integrated circuit being plugged into a powered-up system includes a first circuit ( ) for detecting a hot swap condition, a second circuit ( ) coupled to the first circuit for preventing a pn junction diode ( ) in a pull-up transistor ( ) from going into a forward bias condition, and a third circuit ( ) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.

Multi-Purpose Source Synchronous Interface Circuitry

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US Patent:
7091890, Aug 15, 2006
Filed:
Aug 17, 2004
Appl. No.:
10/919901
Inventors:
Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03M 9/00
US Classification:
341100, 341 59
Abstract:
A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Semiconductor Component Having Test Pads And Method And Apparatus For Testing Same

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US Patent:
7235412, Jun 26, 2007
Filed:
May 11, 2004
Appl. No.:
10/842770
Inventors:
Mohsen Hossein Mardi - Fremont CA, US
Jae Cho - Saratoga CA, US
Xin X. Wu - Fremont CA, US
Chih-Chung Wu - Hsinchu, TW
Shih-Liang Liang - Chung Li, TW
Sanjiv Stokes - Los Altos CA, US
Hassan K. Bazargan - San Jose CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
H01L 21/66
US Classification:
438 14, 438 15, 438 18
Abstract:
A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Semiconductor Component Having Test Pads And Method And Apparatus For Testing Same

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US Patent:
7737439, Jun 15, 2010
Filed:
May 17, 2007
Appl. No.:
11/804391
Inventors:
Mohsen Hossein Mardi - Saratoga CA, US
Jae Cho - Saratoga CA, US
Xin X. Wu - Fremont CA, US
Chih-Chung Wu - Hsinchu, TW
Shih-Liang Liang - Chung Li, TW
Sanjiv Stokes - Los Altos CA, US
Hassan K. Bazargan - San Jose CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
H01L 23/485
US Classification:
257 48, 257673, 257780, 438 14, 438 18
Abstract:
A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Power Management Within An Integrated Circuit

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US Patent:
8612789, Dec 17, 2013
Filed:
Jan 13, 2011
Appl. No.:
13/005994
Inventors:
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
William E. Allaire - West Chester PA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1/26
US Classification:
713324
Abstract:
An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Semiconductor Component Having Test Pads And Method And Apparatus For Testing Same

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US Patent:
20070218573, Sep 20, 2007
Filed:
May 17, 2007
Appl. No.:
11/804496
Inventors:
Mohsen Mardi - Saratoga CA, US
Jae Cho - Saratoga CA, US
Xin Wu - Fremont CA, US
Chih-Chung Wu - , US
Shih-Liang Liang - Chung Li City, TW
Sanjiv Stokes - Los Altos CA, US
Hassan Bazargan - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 21/66
US Classification:
438018000, 257E21521
Abstract:
A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Integrated Circuit With Programmable Circuitry And An Embedded Processor System

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US Patent:
20120221833, Aug 30, 2012
Filed:
Feb 28, 2011
Appl. No.:
13/037234
Inventors:
William E. Allaire - West Chester PA, US
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
Sandeep Dutta - Foster City CA, US
Patrick J. Crotty - San Jose CA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G06F 15/76
G06F 9/06
US Classification:
712 37, 712E09003
Abstract:
An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Frequency Controlled System For Positive Voltage Regulation

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US Patent:
63008394, Oct 9, 2001
Filed:
Aug 22, 2000
Appl. No.:
9/644286
Inventors:
Hassan K. Bazargan - San Jose CA
Farshid Shokouhi - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G05F 140
US Classification:
331 57
Abstract:
In a charge pump system, the frequency of an oscillator is based on the output signals from a plurality of differential amplifiers. Each differential amplifier receives a different reference voltage as well as a common input voltage derived from the pumped voltage. A predetermined logic signal output by the differential amplifiers modifies, i. e. reduces, an original frequency of the oscillator. In this manner, the charge pump system quickly compensates for any overshoot in the pumped voltage in a manner directly correlated to the magnitude of the pumped voltage. If no differential amplifiers output the predetermined logic signal, then the oscillator generates the original frequency. In this manner, the charge pump system also compensates for any undershoot in the pumped voltage by providing the fastest frequency.
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Hassan K Bazargan from Morgan Hill, CA, age ~66 Get Report