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Jae Yoo Phones & Addresses

  • San Jose, CA
  • Germantown, MD

Professional Records

Lawyers & Attorneys

Jae Yoo Photo 1

Jae Wook Yoo - Lawyer

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Licenses:
New York - Currently registered 2007
Education:
Emory

Medicine Doctors

Jae Yoo Photo 2

Jae Y. Yoo

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Specialties:
Internal Medicine, Nephrology
Work:
Jae Y Yoo MD
966 S Western Ave STE 106, Los Angeles, CA 90006
(323) 731-2001 (phone), (323) 731-1482 (fax)
Education:
Medical School
Korea Univ Coll of Med, Chong No Ku, Seoul, So Korea
Graduated: 1982
Procedures:
Bone Marrow Biopsy
Conditions:
Acute Bronchitis
Acute Conjunctivitis
Acute Pancreatitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Languages:
English
Korean
Description:
Dr. Yoo graduated from the Korea Univ Coll of Med, Chong No Ku, Seoul, So Korea in 1982. He works in Los Angeles, CA and specializes in Internal Medicine and Nephrology. Dr. Yoo is affiliated with St Vincent Medical Center.
Jae Yoo Photo 3

Jae H. Yoo

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Specialties:
Anatomic Pathology & Clinical Pathology
Work:
Clinical Pathology Associates
4900 Mueller Blvd, Austin, TX 78723
(512) 579-4000 (phone), (512) 222-0146 (fax)
Education:
Medical School
Seoul Natl Univ, Coll of Med, Chongno Ku, Seoul, So Korea
Graduated: 1972
Languages:
English
Description:
Dr. Yoo graduated from the Seoul Natl Univ, Coll of Med, Chongno Ku, Seoul, So Korea in 1972. He works in Austin, TX and specializes in Anatomic Pathology & Clinical Pathology. Dr. Yoo is affiliated with Baptist Medical Center, Dell Childrens Medical Center, Hospital At Westlake Medical Center and Saint Davids Medical Center.

License Records

Jae Sang Yoo

License #:
21676 - Active
Category:
Architect
Issued Date:
Oct 9, 2009
Expiration Date:
Oct 31, 2017
Organization:
Firm Not Published

Resumes

Resumes

Jae Yoo Photo 4

Principal Engineer

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Location:
208-26 15 Rd, Waterford, CA
Industry:
Computer Software
Work:
Violin Systems Aug 2013 - Jul 2015
Senior Software Engineer

Fortinet Aug 2013 - Jul 2015
Principal Engineer

Accelops Aug 2011 - Aug 2013
Technical Lead

Cisco Feb 2007 - Aug 2011
Senior S and W Engineer

Copacast Mar 2006 - Dec 2006
Senior S and W Engineer
Education:
Kwangwoon University
Bachelors, Electronics Engineering
Skills:
Tcp/Ip
Qos
Embedded Systems
C++
Device Drivers
Ethernet
Linux
Security
Networking
Big Data
Internet Protocol Suite
Software Development
C (Programming Language
Java
Ic
Certifications:
Elastic Certified Engineer
Jae Yoo Photo 5

Jae Yoo

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Jae Yoo Photo 6

Jae Yoo

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Jae Yoo Photo 7

Jae Yoo

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Jae Yoo Photo 8

Jae Yoo

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Jae Yoo Photo 9

Jae Yoo

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Jae Yoo Photo 10

Student At Westwood College

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Location:
Washington D.C. Metro Area
Industry:
Construction
Education:
Westwood College 2008 - 2011
Jae Yoo Photo 11

Jae Yoo

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jae Young Yoo
President
GOLDEN ROCKS, INC
22320 Foothill Blvd STE 322, Hayward, CA 94541
Jae Yong Yoo
ESM TECHNOLOGY INC
Jae Yoo
Manager
Korean Korner, Inc
Ret Groceries
12207 Veirs Ml Rd, Silver Spring, MD 20906
(301) 933-2000, (301) 933-3512
Jae Chan Yoo
Fresh & Natural Cafe 77-2, LLC
Food Service
426 S Main St, Milpitas, CA 95035
Jae Hyoung Yoo
Vice Presi
AJU INVESTMENT HOLDINGS USA INC
Jae S. Yoo
Principal
Young & Seon Corp Inc /Novia T
Nonclassifiable Establishments
7601 Little Riv Tpke, Annandale, VA 22003
Jae Yoo
Principal
Pro Express Movers
Transportation Services
3610 Flora Vis Ave, Santa Clara, CA 95051

Publications

Us Patents

Source Transistor Configurations And Control Methods

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US Patent:
20070063763, Mar 22, 2007
Filed:
Jul 6, 2006
Appl. No.:
11/483263
Inventors:
Jae Yoo - Pleasanton CA, US
Sung Son - Santa Clara CA, US
Myung Choi - San Jose CA, US
Young Kim - San Jose CA, US
Oh Yoon - Santa Clara CA, US
Sang-Kyun Han - Sunnyvale CA, US
International Classification:
G05F 1/10
US Classification:
327544000
Abstract:
Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Adaptive Resource Provisioning For A Multi-Tenant Distributed Event Data Store

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US Patent:
20210286652, Sep 16, 2021
Filed:
Mar 11, 2020
Appl. No.:
16/815172
Inventors:
- Sunnyvale CA, US
Partha Bhattacharya - Cupertino CA, US
Jae Yoo - Morgan Hill CA, US
Assignee:
Fortinet, Inc. - Sunnyvale CA
International Classification:
G06F 9/50
G06F 9/54
G06F 9/48
G06F 9/38
G06F 16/182
G06F 16/27
H04L 29/06
Abstract:
Systems and methods for adaptively provisioning a distributed event data store of a multi-tenant architecture are provided. According to one embodiment, a managed security service provider (MSSP) maintains a distributed event data store on behalf of each tenant of the MSSP. For each tenant, the MSSP periodically determines a provisioning status for a current active partition of the distributed event data store of the tenant. Further, when the determining indicates an under-provisioning condition exits, the MSSP dynamically increases number of resource provision units (RPUs) to be used for a new partition to be added to the partitions for the tenant by a first adjustment ratio. While, when the determining indicates an over-provisioning condition exists, the MSSP dynamically decreases the number of RPUs to be used for subsequent partitions added to the partitions for the tenant by a second adjustment ratio.

Systems And Methods For Laser Processing Of Solid-State Batteries

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US Patent:
20210245296, Aug 12, 2021
Filed:
Feb 6, 2020
Appl. No.:
16/783910
Inventors:
- Livermore CA, US
John ROEHLING - Livermore CA, US
Jae Hyuck YOO - Dublin CA, US
International Classification:
B23K 26/0622
H01M 8/124
Abstract:
The present disclosure relates to a system for laser processing of a ceramic electrolyte material. The system may include a controller, a laser responsive to the controller for generating a beam, and a beam forming subsystem. The beam forming subsystem controls a parameter of the beam generated by the laser. The beam forming subsystem further controls the beam to provide a laser fluence sufficient to produce densification of the ceramic electrolyte material.

Method For Fast Loading Substrates In A Flat Panel Tool

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US Patent:
20210149308, May 20, 2021
Filed:
Jan 25, 2021
Appl. No.:
17/157634
Inventors:
- Santa Clara CA, US
Preston FUNG - Daly City CA, US
Sean SCREWS - San Jose CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
International Classification:
G03F 7/20
Abstract:
The present disclosure generally relates to a method and apparatus for loading, processing, and unloading substrates. A processing system comprises a load/unload system coupled to a photolithography system. The load/unload system comprises a first set of tracks having a first height and a first width, and a second set of tracks having a second height and a second width different than the first height and first width. An unprocessed substrate is transferred from a lift pin loader to a chuck along the first set of tracks on a first tray while a processed substrate is transferred from the chuck to the lift pin loader along the second set of tracks on a second tray. While a first tray remains with a substrate on the chuck during processing, the load/unload system is configured to unload a processed substrate and load an unprocessed substrate on a second tray.

Dynamic Cooling Control For Thermal Stabilization For Lithography System

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US Patent:
20210011390, Jan 14, 2021
Filed:
Sep 28, 2020
Appl. No.:
17/035105
Inventors:
- Santa Clara CA, US
David Michael CORRIVEAU - Sacramento CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
WeiMin TAO - Palo Alto CA, US
Antoine P. MANENS - Saratoga CA, US
International Classification:
G03F 7/20
Abstract:
Embodiments described herein provide a system, a software application, and methods of a lithography process that provide at least one of the ability to decrease the stabilization time and write an exposure pattern into a photoresist on a substrate compensating for the change in the total pitch over a stabilization time. One embodiment of the system includes a slab, a stage disposed over the slab, a pair of supports disposed on the slab, a processing apparatus, and a chiller system. The pair of supports support a pair of tracks and the stage is configured to move along the pair of tracks. The processing apparatus has an apparatus support coupled to the slab and a processing unit supported by the apparatus support. The processing unit has a plurality of image projection systems. The chiller system has at least one fluid channel disposed in each track of the pair of tracks.

Dynamic Cooling Control For Thermal Stabilization For Lithography System

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US Patent:
20200272063, Aug 27, 2020
Filed:
Feb 25, 2019
Appl. No.:
16/284516
Inventors:
- Santa Clara CA, US
David Michael CORRIVEAU - Sacramento CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
WeiMin TAO - Palo Alto CA, US
Antoine P. MANENS - Saratoga CA, US
International Classification:
G03F 7/20
Abstract:
Embodiments described herein provide a system, a software application, and methods of a lithography process that provide at least one of the ability to decrease the stabilization time and write an exposure pattern into a photoresist on a substrate compensating for the change in the total pitch over a stabilization time. One embodiment of the system includes a slab, a stage disposed over the slab, a pair of supports disposed on the slab, a processing apparatus, and a chiller system. The pair of supports support a pair of tracks and the stage is configured to move along the pair of tracks. The processing apparatus has an apparatus support coupled to the slab and a processing unit supported by the apparatus support. The processing unit has a plurality of image projection systems. The chiller system has at least one fluid channel disposed in each track of the pair of tracks.

Method For Fast Loading Substrates In A Flat Panel Tool

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US Patent:
20200103760, Apr 2, 2020
Filed:
Sep 28, 2018
Appl. No.:
16/146054
Inventors:
- Santa Clara CA, US
Preston FUNG - Santa Clara CA, US
Sean SCREWS - Santa Clara CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
International Classification:
G03F 7/20
Abstract:
The present disclosure generally relates to a method and apparatus for loading, processing, and unloading substrates. A processing system comprises a load/unload system coupled to a photolithography system. The load/unload system comprises a first set of tracks having a first height and a first width, and a second set of tracks having a second height and a second width different than the first height and first width. An unprocessed substrate is transferred from a lift pin loader to a chuck along the first set of tracks on a first tray while a processed substrate is transferred from the chuck to the lift pin loader along the second set of tracks on a second tray. While a first tray remains with a substrate on the chuck during processing, the load/unload system is configured to unload a processed substrate and load an unprocessed substrate on a second tray.

Interferometry System And Methods For Substrate Processing

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US Patent:
20200011652, Jan 9, 2020
Filed:
Jul 3, 2018
Appl. No.:
16/026982
Inventors:
- Santa Clara CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
Glen Alan GOMES - San Jose CA, US
David Michael CORRIVEAU - Sacramento CA, US
Thang Duc NGUYEN - Milpitas CA, US
International Classification:
G01B 9/02
G03F 7/20
Abstract:
Processing systems and methods used in the manufacturing of flat panel displays (FPDs) are provided herein. In one embodiment, a processing system features a motion stage movably disposed on a base surface, one or more X-position interferometers, and a plurality of Y-position interferometers. The X-position interferometers include an X-position mirror fixedly coupled to the motion stage and an X-axis stationary module fixedly coupled a non-moving surface of processing system. Each of the plurality of Y-position interferometers include one of a first or second Y-position mirror fixedly coupled to the motion stage in orthogonal relationship to the one or more X-position mirrors and one of a first or a second Y-axis stationary module fixedly coupled to a non-moving surface of the processing system. Here, each of the Y-axis stationary modules is positioned to direct coherent radiation towards a respective Y-position mirror when the Y-position interferometer thereof is in an active arrangement.
Jae Myung Yoo from San Jose, CA, age ~52 Get Report