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Jody A Fronheiser

from Delmar, NY
Age ~45
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Also known as:
Jody J Fronheiser, Ja Fronheiser, Jane E Fronheiser, Jody A Fronhei
Phone and address:
112 Union Ave, Bethlehem, NY 12054
(518) 439-5456
Related to:
Cathrine M Fronheiser, 69M Nardone, 34Madison C Nardone, 34Virginia FronheiserDiane H Nardone, 68William A Nardone, 70Linda G Colwell, 76Edward R LatulippeChase Nardone, 33Jane E Fronheiser, 45William A Fronheiser, 77William C Nardone, 33William R Colwell, 75William R Colwell, 59
Connected to:
Tina M Fronheiser, 56Richard L Froning, 60Joel O Fronk, 63Pamela J Fronk, 45Sharon E Fronk, 30Shirley L Fronk, 67Catherine S FrontczakOdalys P Frontela, 64Paul J Frontera, 49Carol L Frontiero, 68

Jody Fronheiser Phones & Addresses

  • 112 Union Ave, Delmar, NY 12054 (518) 439-5456
  • 52 Peel St, Selkirk, NY 12158 (518) 439-5456
  • 68 Allen St, Albany, NY 12208 (518) 489-9463
  • 62 Chase Rd, Wallkill, NY 12589 (845) 895-1036 (845) 895-2192
  • Kingston, NY
  • Feura Bush, NY
  • New Paltz, NY
  • Saint Augustine, FL
  • Long Valley, NJ

Work

Company: Dynamic systems inc Jan 2019 Position: Business and contract test development engineer

Education

Degree: Master of Science, Masters School / High School: Clarkson University 2007 to 2010 Specialities: Electrical Engineering

Skills

Epitaxy • Semiconductors • Research • Field Service • Integration

Industries

Semiconductors

Resumes

Resumes

Jody Fronheiser Photo 1

Business And Contract Test Development Engineer

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Location:
1 Elizabeth Ct, New York
Industry:
Semiconductors
Work:
Dynamic Systems Inc
Business and Contract Test Development Engineer
Globalfoundries Jul 2011 - Nov 2018
Member Technical Staff
Ge Global Research Aug 2003 - Jul 2011
Semiconductor and Materials Research Engineer
Emcore Corporation Jun 2000 - Aug 2003
Field Service and East Coast Regional Engineer
Education:
Clarkson University 2007 - 2010
Master of Science, Masters, Electrical Engineering Clarkson University 1996 - 2000
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Epitaxy
Semiconductors
Research
Field Service
Integration

Publications

Us Patents

Method For Fabricating Silicon Carbide Vertical Mosfet Devices

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US Patent:
7691711, Apr 6, 2010
Filed:
Jan 31, 2008
Appl. No.:
12/023369
Inventors:
Zachary Matthew Stum - Niskayuna NY, US
Kevin Sean Matocha - Rexford NY, US
Jody Alan Fronheiser - Selkirk NY, US
Ljubisa Dragoljub Stevanovic - Clifton Park NY, US
Assignee:
General Electric Company - Niskayuna NY
International Classification:
H01L 21/336
US Classification:
438268, 438607, 257328, 257E29118, 257E29121, 257E2141
Abstract:
A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.

Nanostructure Arrays And Methods For Forming Same

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US Patent:
7850941, Dec 14, 2010
Filed:
Oct 20, 2006
Appl. No.:
11/551305
Inventors:
Loucas Tsakalakos - Niskayuna NY, US
Bastiaan A. Korevaar - Schenectady NY, US
Joleyn E. Balch - Schaghticoke NY, US
Jody A. Fronheiser - Selkirk NY, US
Reed R. Corderman - Niskayuna NY, US
Fred Sharifi - Niskayuna NY, US
Vidya Ramaswamy - Niskayuna NY, US
Assignee:
General Electric Company - Niskayuna NY
International Classification:
C01B 31/00
C01B 31/02
US Classification:
423445R, 977891, 977890, 977888, 977893, 4234473
Abstract:
A method for forming an array of elongated nanostructures, includes in one embodiment, providing a substrate, providing a template having a plurality of pores on the substrate, and removing portions of the substrate under the plurality of pores of the template to form a plurality of cavities. A catalyst is provided in the plurality of cavities in the substrate, and the pores of the template are widened to expose the substrate around the catalyst so that the catalyst is spaced from the sides of the plurality of pores of the template. A plurality of elongated nanostructures is grown from the catalyst spaced from the sides of the pores of the template.

Dimension Profiling Of Sic Devices

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US Patent:
7906427, Mar 15, 2011
Filed:
Oct 14, 2008
Appl. No.:
12/251341
Inventors:
Jody Alan Fronheiser - Selkirk NY, US
Peter Micah Sandvik - Niskayuna NY, US
Kevin Sean Matocha - Rexford NY, US
Vinayak Tilak - Niskayuna NY, US
Assignee:
General Electric Company - Niskayuna NY
International Classification:
H01L 21/4763
US Classification:
438622
Abstract:
There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.

Semiconductor Devices And Systems

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US Patent:
8198650, Jun 12, 2012
Filed:
Dec 8, 2008
Appl. No.:
12/329841
Inventors:
Stanislav Ivanovich Soloviev - Albany NY, US
Ho-Young Cha - Seoul, KR
Peter Micah Sandvik - Niskayuna NY, US
Alexey Vert - Schenectady NY, US
Jody Alan Fronheiser - Selkirk NY, US
Assignee:
General Electric Company - Niskayuna NY
International Classification:
H01L 29/66
US Classification:
257104, 257291, 257292, 257438, 257E31063
Abstract:
A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.

Methods Of Forming Finfet Devices With Alternative Channel Materials

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US Patent:
8580642, Nov 12, 2013
Filed:
May 21, 2012
Appl. No.:
13/476645
Inventors:
Witold P. Maszara - Morgan Hill CA, US
Ajey P. Jacob - Albany NY, US
Nicholas V. LiCausi - Watervliet NY, US
Jody A. Fronheiser - Delmar NY, US
Kerem Akarvardar - Saratoga Springs NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/336
H01L 21/84
H01L 21/00
US Classification:
438283, 438157, 438197, 438268
Abstract:
One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

Power Devices And Methods Of Manufacture

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US Patent:
20060267021, Nov 30, 2006
Filed:
May 27, 2005
Appl. No.:
11/141605
Inventors:
Larry Rowland - Scotia NY, US
Jody Fronheiser - Selkirk NY, US
International Classification:
H01L 29/15
US Classification:
257077000
Abstract:
A power device includes at least one n-type semiconductor layer and at least one p-type silicon carbide epitaxial layer comprising gallium acceptors. Another power device includes at least one epitaxial silicon carbide layer and at least one p-type region formed epitaxially in the epitaxial silicon carbide layer. The p-type region comprises gallium acceptors. A method for forming a semiconductor device includes forming a first conductivity type semiconductor layer on a substrate, forming a second conductivity type semiconductor layer on the first conductivity type semiconductor layer. At least one of the semiconductor layers comprises silicon carbide, and one of the forming steps comprises epitaxially doping the respective silicon carbide layer with gallium acceptors.

Method For Fabricating Silicon Carbide Vertical Mosfet Devices

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US Patent:
20080050876, Feb 28, 2008
Filed:
Aug 23, 2006
Appl. No.:
11/466488
Inventors:
Kevin Sean Matocha - Rexford NY, US
Jody Alan Fronheiser - Selkirk NY, US
Larry Burton Rowland - Scotia NY, US
Jesse Berkley Tucker - Niskayuna NY, US
Stephen Daley Arthur - Glenville NY, US
Zachary Matthew Stum - Niskayuna NY, US
Assignee:
GENERAL ELECTRIC COMPANY - Schenectady NY
International Classification:
H01L 21/336
US Classification:
438269
Abstract:
A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Method For Fabricating Silicon Carbide Vertical Mosfet Devices

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US Patent:
20090267141, Oct 29, 2009
Filed:
Jul 7, 2009
Appl. No.:
12/498630
Inventors:
Kevin Sean Matocha - Rexford NY, US
Jody Alan Fronheiser - Selkirk NY, US
Larry Burton Rowland - Scotia NY, US
Jesse Berkley Tucker - Niskayuna NY, US
Stephen Daley Arthur - Glenville NY, US
Zachary Matthew Stum - Niskayuna NY, US
Assignee:
GENERAL ELECTRIC COMPANY - Schenectady NY
International Classification:
H01L 29/78
H01L 21/22
US Classification:
257329, 438510, 257E21135, 257E29257
Abstract:
A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.
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Jody A Fronheiser from Delmar, NY, age ~45 Get Report