John Tse from 519 Kirkham St, San Francisco, CA 94122, Phone: (415) 664-7959

Public records

Vehicle Records

John Tse

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Address:

1130 Plymouth Ave, San Francisco, CA 94112

VIN:

1FAHP32N79W202021

Make:

FORD

Model:

FOCUS

Year:

2009

Resumes

Web Developer

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Location:

San Francisco, CA

Industry:

Education Management

Work:

Unicef Usa
Web Developer

Interests:

Social Services
Children
Economic Empowerment
Politics
Education
Poverty Alleviation
Disaster and Humanitarian Relief
Human Rights
Animal Welfare
Arts and Culture
Health

Languages:

Cantonese
Spanish
English

Senior Staff R And D Engineer

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Location:

Berkeley, CA

Industry:

Computer Software

Work:

Synopsys
Senior Staff R and D Engineer
Altera Jun 1993 - Aug 2009
Member of Technical Staff, Software Engineer

Education:

University of California, Berkeley 1992 - 1993
Master of Science, Masters, Computer Science University of California, Berkeley 1988 - 1992
Bachelors, Bachelor of Science

Skills:

Algorithms
Perl
C++
Tcl
Computer Architecture
Logic Synthesis
Software Engineering

Owner

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Location:

San Francisco, CA

Industry:

Construction

Work:

Owner

John Tse

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John Tse

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John Tse

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Skills:

Microsoft Office
Powerpoint

John Tse

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Location:

United States

Business Records

Name / Title

Company / Classification

Phones & Addresses

John Tse
Manager

Bay Area Business Group on Health
Miscellaneous Publishing

221 Main St, San Francisco, CA 94105

John Tse
Owner

Tse, John
Residential Construction

1159 Fernandez Way, Sharp Park, CA 94044
(650) 280-0154

John Tse
President

IN-SPIRIT CHRISTIAN MINISTRY, INC
Business Services at Non-Commercial Site · Religious Organization

887 Cpe York Pl, San Jose, CA 95133

John Tse
Teacher

Berryessa Union School District
Bus Terminal/Service Facility

945 Piedmont Rd, San Jose, CA 95132
(408) 923-1890

John Tse

Ccc Property Management, LLC

PO Box 184, Orinda, CA 94563

John Tse
Manager

Bay Area Business Group On Health
Health/Allied Services · Book Publishers

221 Main St, San Francisco, CA 94105
(415) 281-9066

John L. Tse
President

ADV CONCEPTS, INC

2508 Ulloa St, San Francisco, CA 94116

John Tse
President

IN-SPIRIT CHRISTIAN MUSIC, INC

887 Cpe York Pl, San Jose, CA 95133
1729 Fumia Ct, San Jose, CA 95131

John Tse
Manager

Bay Area Business Group on Health
Miscellaneous Publishing

221 Main St, San Francisco, CA 94105

Publications

Us Patents

Integrated Circuit Reconfiguration Techniques

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US Patent:

8183883, May 22, 2012

Filed:

Apr 16, 2010

Appl. No.:

12/762295

Inventors:

Chee Seng Tan - Tarman Tanjung, MY
Chai Sia Tan - Bukit Gambir, MY
Elden Chau - San Jose CA, US
John Tse - San Jose CA, US
Neville Carvalho - Campbell CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177
G06F 7/38

US Classification:

326 39, 326 41, 710 13

Abstract:

A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.

Method And Apparatus For Circuit Block Reconfiguration Eda

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US Patent:

8595670, Nov 26, 2013

Filed:

Mar 8, 2010

Appl. No.:

12/719298

Inventors:

John Tse - San Jose CA, US
Neville Carvalho - Campbell CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716116, 716100, 716103, 716104, 716117

Abstract:

Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

Gain Matrix For Hierarchical Circuit Partitioning

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US Patent:

62126687, Apr 3, 2001

Filed:

May 27, 1997

Appl. No.:

8/863880

Inventors:

John Tse - El Cerrito CA
Fung Fung Lee - Milpitas CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 7

Abstract:

A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.

Fitting For Incremental Compilation Of Electronic Designs

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US Patent:

61029645, Aug 15, 2000

Filed:

Oct 27, 1997

Appl. No.:

8/958436

Inventors:

John Tse - El Cerrito CA
Fung Fung Lee - Milpitas CA
David Wolk Mendel - Sunnyvale CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design. " The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions. If this fails, the compiler allows logic cells from the unchanged portion of the changed electronic design to shift by a limited amount to other logic elements within the target hardware device. At first, this shifting is fairly constrained in order to preserve as much of the original compilation's placement as possible.

Hierarchical Circuit Partitioning Using Sliding Windows

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US Patent:

6301694, Oct 9, 2001

Filed:

Sep 24, 1997

Appl. No.:

8/936112

Inventors:

Fung Fung Lee - Milpitas CA
John Tse - El Cerrito CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 11

Abstract:

Systems and methods of hierarchical circuit partitioning are provided. More specifically, the invention utilizes a sliding window which is moved over portions of a hierarchical structure representing a programmable logic device. The window includes some but not all containers of the hierarchical structure so that logic cells may be partitioned within the window. After the logic cells are partitioned in the window, the window is moved to a different location of the hierarchical structure. By utilizing a sliding window, the invention is able to recursively partition logic cells into portions of the hierarchical structure which increases the overall efficiency of the partitioning.

Dual Function Antenna

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US Patent:

42452228, Jan 13, 1981

Filed:

Sep 15, 1978

Appl. No.:

5/942859

Inventors:

Edward Eng - San Jose CA
Glen D. Gibbons - San Jose CA
David L. Thomas - Mountain View CA
John W. Tse - Sunnyvale CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01Q 128

US Classification:

343708

Abstract:

A dual function antenna operating at two frequency bands for both the radar uzing function and the telemetry function with a single antenna cavity. A pair of flush-mounted, cavity-backed circumferential slots are located near the base of a missile body and are fed out-of-phase to produce an N=1 mode gain pattern with peaks at nose-on and aft aspects. Each slot is excited by a probe and tee-bar transition. A telemetry band trap circuit is incorporated into the radar band probe and tee-bar to isolate telemetry band energy. A single telemetry probe is inserted into the cavity and spaced apart from the radar probe to excite the antenna at telemetry frequencies.

Programmable Logic Array Integrated Circuit Devices With Flexible Carry Chains

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US Patent:

56315767, May 20, 1997

Filed:

Sep 1, 1995

Appl. No.:

8/522554

Inventors:

Fung F. Lee - Milpitas CA
John Tse - El Cerrito CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

A programmable logic array integrated circuit has a plurality of logic modules, each of which is programmable to perform any of several logic functions. One such function is the performance of one place of binary addition yielding a sum out signal and a carry out signal. In addition to a dedicated carry chain which conveys the carry out signal of each logic module to the carry in input of another predetermined logic module, circuitry is provided for allowing the carry out signal of each logic module to be alternatively routed through the more general interconnection circuitry of the device. This increases the flexibility of routing of the carry out signals, thereby increasing the flexibility of use of the integrated circuit. Improved circuitry for handling a carry in signal may also be provided in each logic module.

Methods For Partitioning Circuits In Order To Allocate Elements Among Multiple Circuit Groups

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US Patent:

56597177, Aug 19, 1997

Filed:

Jul 31, 1995

Appl. No.:

8/508401

Inventors:

John Tse - El Cerrito CA
David W. Mendel - Sunnyvale CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

395500

Abstract:

Improved circuit partitioning methods are provided which combine the advantage of multiple starting positions of the random initial placement approach with the advantage of optimal starting positions of the greedy initial placement approach, by starting with greedy initial placement and modifying partitioning constraints on subsequent passes so that each pass begins in a new position, In addition, the partitioning goals of interconnection minimization and resource utilization efficiency may be prioritized according to a design goal by manipulating the manner in which partitioning constraints are changed during each partitioning pass. Furthermore a user may adjust the weight of the benefits for eliminating existing interconnections and the weight of the penalties for adding new interconnections in accordance with a design goal.