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Jon K Gibbons

from Windsor, CA
Age ~63
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Also known as:
John Gibbons
Phone and address:
842 Pulteney Pl, Windsor, CA 95492
(707) 974-8464
Related to:
Gabrielle Kimberly Gibson, 44Mark Gibbons, 65Shawn M Gibbons, 40Brittania L Gibbons, 43Stacey J Gibbons, 64Megan E Gibbons, 37Barbara L Gibbons, 93Tiffany J Gibbons, 41Christia V Gibbons, 65
Connected to:
Alexa R Gibbons, 33Andre D Gibbons, 46Chester A Gibbons, 63Eugene F Gibbons, 97Jason B Gibbons, 51Justine H Gibbons, 60Louann Gibbons, 60Lucy H Gibbons, 69Maritza Gibbons, 62Nichole R Gibbons, 37

Jon Gibbons Phones & Addresses

  • 842 Pulteney Pl, Windsor, CA 95492 (707) 974-8464
  • South San Francisco, CA
  • San Francisco, CA
  • Santa Rosa, CA
  • Elk Grove, CA

Work

Company: Fleit Gibbons Gutman Bongini & Bianco P.L. Address:

Specialities

Intellectual Property • Patents • Trademarks • Copyrights • Software Licensing • Computer Law • Internet Law

Professional Records

Lawyers & Attorneys

Jon Gibbons Photo 1

Jon Gibbons - Lawyer

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Office:
Fleit Gibbons Gutman Bongini & Bianco P.L.
Specialties:
Intellectual Property
Patents
Trademarks
Copyrights
Software Licensing
Computer Law
Internet Law
ISLN:
913057931
Admitted:
1998
University:
Rutgers University, B.S.E.E., 1984; Syracuse University, 1991
Law School:
University of Miami, J.D., 1997

Resumes

Resumes

Jon Gibbons Photo 2

Principle Member Of Technical Staff At Oracle America, Inc

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Location:
San Francisco Bay Area
Industry:
Computer Software
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Jon Gibbons

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Jon Gibbons

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Jon Gibbons

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Location:
United States
Jon Gibbons Photo 6

Jon Gibbons

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jon Gibbons
Vice President of Engineering, Chief Technology Officer
Ubicom Inc
Semiconductor and Related Device Manufacturing
510 N Pastoria Ave, Sunnyvale, CA 94085
(408) 789-2200

Publications

Amazon

The Handbook Of Organizational Economics

The Handbook of Organizational Economics

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In even the most market-oriented economies, most economic transactions occur not in markets but inside managed organizations, particularly business firms. Organizational economics seeks to understand the nature and workings of such organizations and their impact on economic performance. This landma...
Binding

Hardcover

Pages

1248

Publisher

Princeton University Press

ISBN #

0691132798

EAN Code

9780691132792

ISBN #

7

Homefront Villains: Amazing Stories Of World War Ii

Homefront Villains: Amazing Stories of World War II

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While our soldiers fight the enemy on the Front Lines of this Great War, our Homefront is under attack by Saboteurs, Gansters, and Super-powered Criminals of all types! Who will stand up to these Homefront Villains!? Jump into the action and defend America's Homefront during World War II! These vil...
Author

Steve Perrin

Binding

Paperback

Pages

30

Publisher

James Dawsey

ISBN #

0985881526

EAN Code

9780985881528

ISBN #

4

Halt Evil Doer!

Halt Evil Doer!

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A detailed guide to the Heroic Earth setting for all your superhero gaming needs! Containing new alien races, new cities, new foreign countries, new planets, new dimensions, new secret societies, a host of new super heroes, and new villains! Halt Evil Doer! contains an in-character guide to crime fi...
Author

C.T. Phipps, Michael Suttkus, Mike Lafferty

Binding

Paperback

Pages

214

Publisher

Phipps Gaming Studios

ISBN #

0615337112

EAN Code

9780615337111

ISBN #

3

Us Patents

Data Synchronizer For A Multiple Rate Clock Source And Method Thereof

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US Patent:
6529570, Mar 4, 2003
Filed:
Sep 30, 1999
Appl. No.:
09/409768
Inventors:
Steven C. Miller - Livermore CA
Michael B. Galles - Los Altos CA
David M. Parry - San Jose CA
Jon C. Gibbons - San Francisco CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
H04L 700
US Classification:
375354, 375355, 375371
Abstract:
A data synchronizer ( ) receives a data ready signal ( ) at a selector ( ). The selector ( ) selects either the data ready signal ( ) or a delayed version of the data ready signal ( ) in response to a speed select signal ( ) determined according to a clock speed of a receive core clock ( ). The selector ( ) provides a select signal ( ) to a first latch unit ( ) and a second latch unit ( ). The first latch unit ( ) generates a latched select signal (A) that is provided as a receive data valid signal ( ) by a signal generator ( ) in response to a slow clock rate for the receive core clock ( ). The second latch unit ( ) generates a delayed select signal (B) that is used by the signal generator ( ) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal ( ) in response to a fast clock rate for the receive core clock ( ).

Display Memory Cache

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US Patent:
60783168, Jun 20, 2000
Filed:
May 3, 1995
Appl. No.:
8/434285
Inventors:
Rich Page - Los Altos Hills CA
James Wiseman - Palo Alto CA
Jon Gibbons - San Francisco CA
Assignee:
Canon Kabushiki Kaisha - Tokyo
International Classification:
G09G 318
US Classification:
345204
Abstract:
An optimized refresh strategy for increasing bandwidth of an LCD. The present invention results in an LCD suitable for dynamic display of information. In the present invention, a display memory is used to store display data generated by a CPU and to provide that data to an LCD. All data writes to the display memory by the CPU are tracked and rows or columns that contain modified data are tagged. These tags may be "set" by mapping the display memory write addresses to row or column numbers. The tags are examined and mapped back into the display memory addresses and only those rows or columns containing changed data are transferred to the data stream for display. As a result, only the information that is changed in the display memory is sent to the display and the dynamic bandwidth of the display is maximized. The refresh in the present invention can be either row-based or column-based.
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Jon K Gibbons from Windsor, CA, age ~63 Get Report