Kazi Azi Asaduzzaman

7149914, Dec 12, 2006

Sep 26, 2003

10/672901

Kazi Asaduzzaman - Milpitas CA, US
Wilson Wong - San Francisco CA, US

Altera Corporation - San Jose CA

G06F 1/04
G06F 1/06
G06F 1/08
G06F 1/24

713500, 713501, 713503

Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e. g. , jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

7352835, Apr 1, 2008

Sep 22, 2003

10/668900

Kazi Asaduzzaman - Milpitas CA, US
Wilson Wong - San Francisco CA, US

Altera Corporation - San Jose CA

H04L 7/02

375359, 375371

Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

7355449, Apr 8, 2008

Feb 1, 2006

11/345709

Thungoc Tran - San Jose CA, US
Kazi Asaduzzaman - Fremont CA, US
Wilson Wong - San Francisco CA, US
Mei Luo - San Jose CA, US
Rakesh Patel - Cupertino CA, US

Altera Corporation - San Jose CA

H03K 19/094

326 82, 326 83, 326 84, 326 85, 326 86

Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

7532029, May 12, 2009

Apr 18, 2007

11/737079

Kazi Asaduzzaman - Fremont CA, US
Leon Zheng - Santa Clara CA, US
Tim Tri Hoang - San Jose CA, US

Altera Corporation - San Jose CA

H03K 19/173
H03L 7/00

326 38, 326 16, 327147

Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

7555087, Jun 30, 2009

Feb 7, 2008

12/027909

Kazi Asaduzzaman - Milpitas CA, US
Wilson Wong - San Francisco CA, US

Altera Corporation - San Jose CA

H04L 7/02

375359, 375371

Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

7557615, Jul 7, 2009

Feb 8, 2008

12/069353

Thungoc M. Tran - San Jose CA, US
Kazi Asaduzzaman - Fremont CA, US
Wilson Wong - San Francisco CA, US
Mei Luo - San Jose CA, US
Rakesh H. Patel - Cupertino CA, US

Altera Corporation - San Jose CA

H03K 19/094
H03K 3/00

326 82, 326 83, 326 86, 326 87, 327108, 327109

Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

7602255, Oct 13, 2009

Sep 25, 2007

11/861144

Kang-Wei Lai - Milpitas CA, US
Ninh D. Ngo - Palo Alto CA, US
Kazi Asaduzzaman - Fremont CA, US
Mian Z. Smith - Los Altos CA, US
Wanli Chang - Saratoga CA, US
Tim Tri Hoang - San Jose CA, US

Altera Corporation - San Jose CA

H03L 7/00

331 16, 331 34, 331177 R, 331176, 331175, 331185

A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

7619451, Nov 17, 2009

Feb 3, 2007

11/670971

Tim Tri Hoang - San Jose CA, US
Kazi Asaduzzaman - Fremont CA, US
Wanli Chang - Saratoga CA, US
Mian Z. Smith - Los Altos CA, US
Kang-Wei Lai - Milpitas CA, US
Leon Zheng - Santa Clara CA, US

Altera Corporation - San Jose CA

H03L 7/06

327156, 327146, 327147, 327155, 327163

Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.