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Kevin Lloyd Beaman

from Boise, ID
Age ~51
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Also known as:
Kevin L Beaman, Kevin O Beaman, Kevin Beman, Kevin Bedaman
Phone and address:
4801 S Skyridge Way, Boise, ID 83709
Related to:
Tina F Hall, 57
Connected to:
Allison R Beaman, 40Andrea B Beaman, 56Eileen Beaman, 60Elise R Beaman, 35Jillian S Beaman, 46Ken Beaman, 63Monica H Beaman, 54Pete M Beaman, 42Seth K Beaman, 54Teri L Beaman, 69

Kevin Beaman Phones & Addresses

  • 4801 S Skyridge Way, Boise, ID 83709
  • 4402 Redhawk Ave, Boise, ID 83716 (208) 426-9354
  • Garden Valley, ID
  • 102 Bracken Ln, King, NC 27021 (336) 969-5134
  • 104 Bracken Ln, King, NC 27021 (336) 969-5134
  • Nokesville, VA
  • Raleigh, NC
  • Cary, NC

Work

Company: On semiconductor Feb 2019 Position: Process integration engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: North Carolina State University Specialities: Philosophy

Industries

Semiconductors

Resumes

Resumes

Kevin Beaman Photo 1

Process Integration Engineer

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Location:
Boise, ID
Industry:
Semiconductors
Work:
On Semiconductor
Process Integration Engineer
Micron Technology
Senior Member of Technical Staff
Micron Technology Apr 1999 - Jan 2003
Thin Films Development Lead
Education:
North Carolina State University
Doctorates, Doctor of Philosophy, Philosophy

Publications

Us Patents

Pd-Soi Substrate With Suppressed Floating Body Effect And Method For Its Fabrication

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US Patent:
6437375, Aug 20, 2002
Filed:
Jun 5, 2000
Appl. No.:
09/587190
Inventors:
Kevin L. Beaman - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 31072
US Classification:
257192, 257 19, 257 20
Abstract:
A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Sputtered Insulating Layer For Wordline Stacks

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US Patent:
6455441, Sep 24, 2002
Filed:
Aug 31, 2000
Appl. No.:
09/653596
Inventors:
Kevin L. Beaman - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2131
US Classification:
438778
Abstract:
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Methods Of Forming Flash Field Effect Transistor Gates And Non-Flash Field Effect Transistor Gates

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US Patent:
6589843, Jul 8, 2003
Filed:
Jan 9, 2002
Appl. No.:
10/043430
Inventors:
Kevin L. Beaman - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21336
US Classification:
438261, 438258
Abstract:
Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least a first gate dielectric material received over the first semiconductive material portion, a floating gate material overlying the first gate dielectric material, and a second gate dielectric material received over the floating gate material. The second gate dielectric material comprises silicon nitride. In a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are oxidized effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. Additional implementations are contemplated.

Sputtered Insulating Layer For Wordline Stacks

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US Patent:
6617262, Sep 9, 2003
Filed:
Mar 18, 2002
Appl. No.:
10/100397
Inventors:
Kevin L. Beaman - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2131
US Classification:
438778
Abstract:
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of: A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Dram Cell Constructions

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US Patent:
6639243, Oct 28, 2003
Filed:
Dec 5, 2001
Appl. No.:
10/012233
Inventors:
Fernando Gonzalez - Boise ID
Kevin L. Beaman - Boise ID
John T. Moore - Boise ID
Ron Weimer - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27108
US Classification:
257 68, 257296, 257347
Abstract:
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Methods Of Forming Structures Over Semiconductor Substrates, And Methods Of Forming Transistors Associated With Semiconductor Substrates

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US Patent:
6686298, Feb 3, 2004
Filed:
Jun 22, 2000
Appl. No.:
09/602089
Inventors:
Kevin L. Beaman - Boise ID
John T. Moore - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2131
US Classification:
438775, 438787
Abstract:
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.

Semiconductor Assemblies, Methods Of Forming Structures Over Semiconductor Substrates, And Methods Of Forming Transistors Associated With Semiconductor Substrates

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US Patent:
6690046, Feb 10, 2004
Filed:
Nov 13, 2001
Appl. No.:
09/993109
Inventors:
Kevin L. Beaman - Boise ID
John T. Moore - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2976
US Classification:
257288, 257401, 257900
Abstract:
The invention encompasses semiconductor assemblies that include a semiconductor substrate having a first region and a second region defined therein. A first oxide region is on the substrate and covers the first region of the substrate. The first oxide region has nitrogen provided therein and substantially all of the nitrogen is at least 10 above the semiconductor substrate. A first conductive layer is over the first oxide region and defines a first transistor gate. First source/drain regions are proximate the first transistor gate and gatedly connected to one another by the first transistor gate. The second region is covered by a second oxide region. A second conductive layer is over the second oxide region and defines a second transistor gate. Second source/drain regions are proximate the second transistor gate and gatedly connected to one another by the second transistor gate.

Dram Cell Constructions

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US Patent:
6707090, Mar 16, 2004
Filed:
Mar 20, 2003
Appl. No.:
10/393696
Inventors:
Fernando Gonzalez - Boise ID
Kevin L. Beaman - Boise ID
John T. Moore - Boise ID
Ron Weimer - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27108
US Classification:
257296, 257401, 257906
Abstract:
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further contains a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
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Kevin Lloyd Beaman from Boise, ID, age ~51 Get Report