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Kevin Nazareth Phones & Addresses

  • San Jose, CA
  • 555 Lockewood Ln, Scotts Valley, CA 95066 (831) 515-7961
  • Cupertino, CA
  • Summit, NJ
  • Houston, TX
  • Santa Clara, CA
  • 4247 Ruby Ave, San Jose, CA 95135 (619) 278-9011

Work

Position: Production Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Kevin Nazareth Photo 1

Kevin Nazareth

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Location:
San Francisco, CA
Industry:
Computer Software
Skills:
Cae
Kevin Nazareth Photo 2

Kevin Nazareth

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Location:
San Francisco, CA
Industry:
Computer Software

Publications

Us Patents

Automated Design Partitioning

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US Patent:
6339836, Jan 15, 2002
Filed:
Aug 24, 1998
Appl. No.:
09/139156
Inventors:
Karl Eisenhofer - San Jose CA
Kevin Nazareth - Scotts Valley CA
Peter Odryna - Santa Cruz CA
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
G06F 1750
US Classification:
716 5
Abstract:
A flexible and extensible automated design partitioning mechanism that facilitates simulation sessions employing two or more simulators is provided. A simulation backplane includes partitioning logic that identifies the design blocks of an overall design pertaining to each of a plurality of simulators. Once the partitions have been identified, nets that cross simulator boundaries (e. g. , mixed nets) are determined and inter-simulator connectivity information is generated for the simulators. According to one aspect of the present invention, the partitioning logic is able to accomodate arbitrary (e. g. , instance-based) partitioning. A design source expressed in a design representation upon which a first simulator may operate is received. Design blocks to be partitioned to each of a plurality of solvers are identified based upon one or more partitioning directives and the design source. A first instance of a cell is assigned to a first solver and a second instance of the cell is assigned to a second solver.

Optimizing Runtime Communication Processing Between Simulators

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US Patent:
61084948, Aug 22, 2000
Filed:
Aug 24, 1998
Appl. No.:
9/139215
Inventors:
Karl Eisenhofer - San Jose CA
Arun T. Venkatachar - Sunnyvale CA
Kevin Nazareth - Scotts Valley CA
Peter Odryna - Santa Cruz CA
Robert Michael Bradley - Raleigh NC
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
G06F 9455
US Classification:
39550035
Abstract:
An optimization mechanism for increasing runtime performance in a co-/ multi-simulation environment by reducing the number of connections between simulators is provided. A simulation backplane includes netlist optimization logic that analyzes the netlists of design partitions and employs a set of rules to reduce the number of connections among simulators participating in a simulation session. According to one aspect of the present invention, synchronizations among a first solver and one or more other solvers that are simulating a design of a system or a portion thereof are limited to situations in which simulation being performed by each of the one or more other solvers is dependent upon event information from the first solver. Partitioned design source information is received for each a plurality of solvers. Based upon the partitioned design source information, partition dependency information is generated.
Kevin D Nazareth from San Jose, CA, age ~63 Get Report