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Manas Prachee Behera

from Cedar Park, TX
Age ~45
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Related to:
Rachana Naikade Behera, 45Prachee S Behera, 46Rajanikant BeheraBrachee Behera, 40Aasish Behera, 44Aasish Behera, 45Pravanjan Behera
Connected to:
Amarendra Behera, 44Aswini K Behera, 40Biswajit Behera, 45Mahendra K Behera, 44Namrata BeheraPrahallad BeheraAmit BehereBruce L Behers, 66Mahdieh Beheshti, 45Meredith Behgooy

Manas Behera Phones & Addresses

  • 3908 Remington Rd, Cedar Park, TX 78613 (512) 705-7896
  • 12610 Riata Trace Pkwy, Austin, TX 78727
  • 126 Ridgeview Ln, Yorktown Heights, NY 10598
  • 2101 Grant Ave, Corvallis, OR 97330
  • Mohegan Lake, NY

Resumes

Resumes

Manas Behera Photo 1

Founder

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Location:
Austin, TX
Industry:
Electrical/Electronic Manufacturing
Work:
Intel Corporation Jun 2016 - Jul 2017
Design Manager
Marvell Semiconductor Apr 2013 - Aug 2015
Senior Staff Design Manager
Spearix Technologies Apr 2013 - Aug 2015
Founder
Marvell Semiconductor Dec 2010 - Apr 2013
Staff Rfic Engineer
Qualcomm Nov 2007 - Dec 2010
Senior Analog and Rf Ic Design Engineer
Education:
Oregon State University 2001 - 2004
Masters, Electrical Engineering Oregon State University 1997 - 2001
Bachelors, Electronics, Engineering, Communications
Skills:
Ic
Analog Circuit Design
Analog
Cmos
Semiconductors
Integrated Circuit Design
Soc
Asic
Circuit Design
Mixed Signal
Vlsi
Verilog
Integrated Circuits
Manas Behera Photo 2

Hotel Sales Manager

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Work:
Banglore Computer Education-2001
Hotel Sales Manager
Manas Behera Photo 3

Enterprise Anchor

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Location:
Cedar Park, TX
Work:
Invincix Solutions Private Limited
Enterprise Anchor
Manas Behera Photo 4

Senior Project Manager

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Industry:
Electrical/Electronic Manufacturing
Work:
Lanarsy Infra Limited
Senior Project Manager
Education:
Biju Patnaik University of Technology, Odisha 1996 - 2000
Bachelor of Engineering, Bachelors, Electronics Engineering
Manas Behera Photo 5

Manas Behera

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Manas Behera Photo 6

Manas Behera

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Manas Behera Photo 7

Manas Behera

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Manas Behera Photo 8

Manas Behera

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Publications

Us Patents

Noise-Canceling For Differential Amplifiers Requiring No External Matching

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US Patent:
8310309, Nov 13, 2012
Filed:
May 3, 2010
Appl. No.:
12/772924
Inventors:
Manas Behera - Austin TX, US
Harish S Muthali - Round Rock TX, US
Kenneth Charles Barnett - Austin TX, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03F 3/45
US Classification:
330260, 330255
Abstract:
A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.

Harmonic Suppression And/Or Rejection

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US Patent:
8422975, Apr 16, 2013
Filed:
Jun 9, 2010
Appl. No.:
12/797454
Inventors:
Manas Behera - Austin TX, US
Junxiong Deng - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H04B 1/10
H04B 1/04
US Classification:
455296, 455317, 455310, 4551141, 455323, 455 76
Abstract:
Disclosed are circuits, techniques and methods for removing one or more harmonics from a waveform that has been mixed with a local oscillator. In one particular example, such a waveform may also be mixed with a second local oscillator at a different frequency and combined with the first mixed waveform to suppress and/or substantially remove the one or more harmonics.

Methods And Apparatus For Providing A Built-In Self Test

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US Patent:
8589750, Nov 19, 2013
Filed:
Jul 14, 2010
Appl. No.:
12/836462
Inventors:
Gaurab Banerjee - Karnataka, IN
Manas Behera - Austin TX, US
Kenneth Charles Barnett - Austin TX, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03M 13/00
US Classification:
714733
Abstract:
A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.

Signal Generator For A Built-In Self Test

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US Patent:
20110273197, Nov 10, 2011
Filed:
May 7, 2010
Appl. No.:
12/776168
Inventors:
Gaurab Banerjee - Bangalore, IN
Manas Behera - Austin TX, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G01R 31/3187
G01M 19/00
US Classification:
3247503, 702124
Abstract:
An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.

Highly Accurate True Rms Power Detector For Cellular Applications

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US Patent:
20140118050, May 1, 2014
Filed:
Oct 30, 2013
Appl. No.:
14/067411
Inventors:
- St. Michael, BB
Manas Behera - Cedar Park TX, US
Gregory T. Uehara - Kaneohe HI, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G01R 19/02
US Classification:
327348
Abstract:
New devices and methods capable of detecting a true Root-Mean-Square (RMS) power level of an analog input signal are disclosed. For example, an electronic circuit can include a squaring circuit that receives the analog input signal and processes the analog input signal so as to produce a squared-output of the analog input signal using an analog transfer function of the squaring circuit, and a square-root circuit that receives the squared-output and processes the squared-output using an analog transfer function of the square-root circuit so as to produce an analog RMS output signal representing the true RMS power level of the analog input signal.
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Manas Prachee Behera from Cedar Park, TX, age ~45 Get Report