Manish R Biyani

7768331, Aug 3, 2010

Jan 23, 2008

12/018734

Manish Biyani - Chandler AZ, US

Marvell International Ltd. - Hamilton

H03K 3/289

327202, 327199, 327200, 327201, 327203

A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation. Similarly, a separate always-on power supply powers the slave flip flop and standby mode control circuit during active mode and standby mode operation to enable state retention.

7796445, Sep 14, 2010

Feb 12, 2008

12/029908

Manish Biyani - Chandler AZ, US
Franco Ricci - Chandler AZ, US

Marvell International, Ltd. - Hamilton

G11C 7/00

36518905, 36518508, 365154

A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.

7982514, Jul 19, 2011

Jun 23, 2010

12/821869

Manish Biyani - Chandler AZ, US

Marvell International Ltd. - Hamilton

H03K 3/289

327202, 327203

A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation. Similarly, a separate always-on power supply powers the slave flip flop and standby mode control circuit during active mode and standby mode operation to enable state retention.

20040120182, Jun 24, 2004

Dec 23, 2002

10/329124

Manish Biyani - Chandler AZ, US
Lawrence Clark - Phoenix AZ, US
Shay Demmons - Chandler AZ, US
Franco Ricci - Chandler AZ, US

G11C011/00

365/156000

An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.