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Manjunatha L Gowda

from San Jose, CA
Age ~53
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Also known as:
Manjunath A Gowda
Phone and address:
1056 Oaktree Dr, San Jose, CA 95129
(408) 421-2622
Related to:
Pratibha Harkuni Rajashekar, 47Sowdhamini Gowda, 48Pratibha Rajashekar, 53Channabasappa Gowda, 56
Connected to:
Akhil S Gowda, 30Anuradha K GowdaChaitra Gowda, 35Mahanth K Gowda, 36Manu Gowda, 45Murali Gowda, 57Renuka Gowda, 64Rohan N Gowda, 37Suvarna S Gowda, 50Annabelle A Gowdey, 79

Manjunatha Gowda Phones & Addresses

  • 1056 Oaktree Dr, San Jose, CA 95129 (408) 421-2622
  • 604 Calero Ave, San Jose, CA 95123
  • 1540 Deluca Dr, San Jose, CA 95131
  • Santa Clara, CA
  • Cupertino, CA
  • Chester, PA
  • 1056 Oaktree Dr, San Jose, CA 95129

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Resumes

Resumes

Manjunatha Gowda Photo 1

Senior Software Engineer

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Location:
825 east Evelyn Ave, Sunnyvale, CA 94086
Industry:
Computer Software
Work:
LSI Corporation since Sep 1998
Principal EDA Software Engineer
Integrated Systems Management Inc - Tarrytown NY Dec 1996 - Sep 1998
Sr. Software Enginner
Novell - Bangalore, India May 1995 - Dec 1996
Software Engineer
Accord Software & Systems - Bangalore, India Jun 1994 - May 1995
Software Engineer
Education:
Santa Clara University 1999 - 2001
MS, Computer Engineering National Institute of Technology Karnataka 1990 - 1994
B.Tech, Computer Engineering
Skills:
Verilog
Eda
Soc
Asic
Static Timing Analysis
Perl
Tcl
C++
Unix
Unix Shell Scripting
Linux
Windows
Tcp/Ip
Udp
Yacc
Flex
Apache
Assembly Language
Java
Object Oriented Design
Scala
C
Agile Methodologies
Software Development
Languages:
Kannada
English
Manjunatha Gowda Photo 2

Manjunatha Gowda

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Work:
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Manjunatha Gowda Photo 3

Manjunatha Gowda

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Manjunatha Gowda Photo 4

Manjunatha Gowda

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Publications

Us Patents

Distributed Delay Prediction Of Multi-Million Gate Deep Sub-Micron Asic Designs

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US Patent:
7006962, Feb 28, 2006
Filed:
Nov 29, 2001
Appl. No.:
09/997888
Inventors:
Saket Goyal - Milpitas CA, US
Santhanakrishnan Raman - Mountain View CA, US
Prabhakaran Krishnamurthy - Cupertino CA, US
Prasad Subbarao - San Jose CA, US
Manjunatha Gowda - Santa Clara CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
703 18, 716 2, 716 9, 709107
Abstract:
A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.

Deep Learning Based Identification Of Difficult To Test Nodes

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US Patent:
20210295169, Sep 23, 2021
Filed:
Apr 15, 2021
Appl. No.:
17/231866
Inventors:
- Santa Clara CA, US
Kaushik Narayanun - Los Gatos CA, US
Lijuan Luo - San Jose CA, US
Karthikeyan Natarajan - Bangalore, IN
Manjunatha Gowda - San Jose CA, US
Sandeep Gangundi - Milpitas CA, US
Assignee:
NVIDIA Corp. - Santa Clara CA
International Classification:
G06N 3/08
G06T 1/20
G06T 11/20
G06N 3/04
G06F 30/323
Abstract:
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
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Manjunatha L Gowda from San Jose, CA, age ~53 Get Report