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Mark A Isenberger

from Aston, PA
Age ~61
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Also known as:
Mark Allan Isenberger, Jennifer Isenberger, Mark R
Phone and address:
109 Carriage Ln, Chester, PA 19014
(610) 358-5482
Related to:
Charles A IsenbergerMarie IsenbergerJacqueline Mattison, 88John Rahrig, 93
Connected to:
Andy T Isenberg, 46Casey M Isenberg, 42Jacob K Isenberg, 48Jody L Isenberg, 72Leonard G Isenberg, 77Miranda F Isenberg, 48Perry A Isenberg, 64Shane IsenbergEileen Z Iseneker, 61Christina A Isenhart, 61

Mark Isenberger Phones & Addresses

  • 109 Carriage Ln, Aston, PA 19014 (610) 358-5482
  • 14 Carriage Ln, Aston, PA 19014
  • 78 Dulce Ct, Corrales, NM 87048 (505) 898-1032
  • 7155 Guyer Ave, Philadelphia, PA 19153
  • Springfield, PA
  • 18 Lighthouse Cv, Brigantine, NJ 08203 (609) 266-3152
  • Wilmington, DE
  • Atlantic Hl, NJ
  • Lehighton, PA

Work

Company: Intel corporation Position: Principal engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: University of Illinois at Urbana - Champaign Specialities: Chemical Engineering

Skills

Debugging • Design of Experiments • Semiconductor Industry • Cross Functional Team Leadership • Spc • Process Engineering • Semiconductors • C • Program Management • Manufacturing • Process Improvement

Industries

Semiconductors

Resumes

Resumes

Mark Isenberger Photo 1

Mark Isenberger

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Location:
78 Dulce Ct, Corrales, NM 87048
Industry:
Semiconductors
Work:
Intel Corporation
Principal Engineer
Education:
University of Illinois at Urbana - Champaign
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Debugging
Design of Experiments
Semiconductor Industry
Cross Functional Team Leadership
Spc
Process Engineering
Semiconductors
C
Program Management
Manufacturing
Process Improvement

Publications

Us Patents

Low-Voltage And Interface Damage-Free Polymer Memory Device

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US Patent:
6952017, Oct 4, 2005
Filed:
Jan 21, 2004
Appl. No.:
10/762955
Inventors:
Jian Li - Sunnyvale CA, US
Xiao-Chun Mu - Saratoga CA, US
Mark Isenberger - Corrales NM, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L029/06
US Classification:
257 10, 257295, 257314
Abstract:
One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Polymer Memory Having A Ferroelectric Polymer Memory Material With Cell Sizes That Are Asymmetric

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US Patent:
7084446, Aug 1, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/648538
Inventors:
Mark S. Isenberger - Corrales NM, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/94
US Classification:
257295, 438 3
Abstract:
A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines. As such, only 33% of the machinery has to be upgraded for manufacturing one multi-layer construction. The entire polymer memory has four multi-layer constructions having a total of 12 layers of lines, of which four layers require new-technology machinery. The multi-layer constructions are formed on underlying electronics.

Memory Circuit With Spacers Between Ferroelectric Layer And Electrodes

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US Patent:
7164166, Jan 16, 2007
Filed:
Mar 19, 2004
Appl. No.:
10/804795
Inventors:
Mark S. Isenberger - Corrales NM, US
Ebrahim Andideh - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/76
US Classification:
257295, 257306, 257309, 257310
Abstract:
A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

Metal Heater For In Situ Heating And Crystallization Of Ferroelectric Polymer Memory Film

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US Patent:
7173842, Feb 6, 2007
Filed:
Mar 31, 2004
Appl. No.:
10/816260
Inventors:
Mark S. Isenberger - Corrales NM, US
Hitesh Windlass - Hillsboro OR, US
Wayne K. Ford - Beaverton OR, US
Carlton E Hanna - Marlborough MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/22
US Classification:
365145, 365151, 365 65, 365117
Abstract:
An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

Polymer Memory Having A Ferroelectric Polymer Memory Material With Cell Sizes That Are Asymmetric

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US Patent:
7407819, Aug 5, 2008
Filed:
May 17, 2006
Appl. No.:
11/436209
Inventors:
Mark S. Isenberger - Corrales NM, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/82
H01L 31/119
US Classification:
438 3, 438128, 438240, 438780, 257209, 257295, 257E21002, 257E21208, 365158, 36518513
Abstract:
A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines.

Forming Ferroelectric Polymer Memories

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US Patent:
7727777, Jun 1, 2010
Filed:
May 31, 2002
Appl. No.:
10/160641
Inventors:
Ebrahim Andideh - Portland OR, US
Mark Isenberger - Corrales NM, US
Michael Leeson - Portland OR, US
Mani Rahnama - Beaverton OR, US
International Classification:
H01L 21/00
US Classification:
438 3, 438240, 438238, 438250, 438393, 257E27104
Abstract:
In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.

Low-Voltage And Interface Damage-Free Polymer Memory Device

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US Patent:
20030001176, Jan 2, 2003
Filed:
Jun 29, 2001
Appl. No.:
09/897174
Inventors:
Jian Li - Sunnyvale CA, US
Xiao-Chun Mu - Saratoga CA, US
Mark Isenberger - Corrales NM, US
Assignee:
Intel Corporation
International Classification:
H01L029/76
US Classification:
257/295000, 257/296000, 257/311000
Abstract:
One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Method And Apparatus To Improve Memory Performance

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US Patent:
20050114588, May 26, 2005
Filed:
Nov 26, 2003
Appl. No.:
10/722813
Inventors:
Jonathan Lucker - Portland OR, US
Robert Faber - Hillsboro OR, US
Mark Isenberger - Corrales NM, US
International Classification:
G06F012/00
US Classification:
711103000
Abstract:
Briefly, in accordance with an embodiment of the invention, an apparatus and method to improve memory performance is provided. The method may include performing a read cycle that includes a destructive read operation and a write back operation, wherein the destructive read operation includes reading information from a first memory cell of a memory and wherein the write back operation includes writing the information read from the first memory cell to a second memory cell of the memory.
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Mark A Isenberger from Aston, PA, age ~61 Get Report