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Mark William Reiten

from Alamo, CA
Age ~64
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Also known as:
Mark W Reiten, Mark W Keiten, Mark W Reitan, Mark Reiter
Phone and address:
2342 Royal Oaks Dr, Alamo, CA 94507
(925) 553-7748
Related to:
Donald Miller, 59Terry ReitenLisa A Waypa, 56Ardeen ReitenNancy Atherton, 61
Connected to:
Allen D Reiten, 55Shari A Reitenauer, 61Darrin Reiter, 57Elena Reiter, 50Elmer G Reiter, 91Evan L Reiter, 33Gayle S Reiter, 69Hal F Reiter, 64Marina V Reiter, 50Melissa H Reiter, 55

Mark Reiten Phones & Addresses

  • 2342 Royal Oaks Dr, Alamo, CA 94507 (925) 553-7748
    • s
  • 4000 Anderson Rd #59, Nashville, TN 37217
  • 3 Spring Valley Ln, Millbrae, CA 94030
  • Santa Clara, CA
  • San Francisco, CA
  • Minneapolis, MN
  • Homewood, CA
  • 2342 Royal Oaks Dr, Alamo, CA 94507

Work

Position: Service Occupations

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mark Reiten
President
REITEN ENTERPRISES, INCORPORATED
3 Spg Vly Ln, Millbrae, CA 94030
Mark Reiten
President
VIQUANT
Business Services at Non-Commercial Site
3 Spg Vly Ln, Millbrae, CA 94030

Publications

Us Patents

Output Circuit For Analog Neural Memory In A Deep Learning Artificial Neural Network

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US Patent:
20220374161, Nov 24, 2022
Filed:
Aug 31, 2021
Appl. No.:
17/463063
Inventors:
- San Jose CA, US
Thuan Vu - San Jose CA, US
Mark Reiten - Alamo CA, US
International Classification:
G06F 3/06
G06N 3/08
Abstract:
Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W− bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.

Precise Data Tuning Method And Apparatus For Analog Neural Memory In An Artificial Neural Network

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US Patent:
20220374699, Nov 24, 2022
Filed:
Jul 27, 2022
Appl. No.:
17/875281
Inventors:
- San Jose CA, US
Steven Lemke - Boulder Creek CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US
Mark Reiten - Alamo CA, US
International Classification:
G06N 3/063
G11C 11/54
G06F 1/03
G06F 17/16
G11C 11/56
G06F 11/16
G11C 13/00
G11C 29/44
G06F 7/78
Abstract:
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

Input Function Circuit Block And Output Neuron Circuit Block Coupled To A Vector-By-Matrix Multiplication Array In An Artificial Neural Network

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US Patent:
20230031487, Feb 2, 2023
Filed:
Sep 21, 2022
Appl. No.:
17/949962
Inventors:
- San Jose CA, US
Steven Lemke - Boulder Creek CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US
Mark Reiten - Alamo CA, US
International Classification:
H01L 27/11531
G11C 16/04
G06N 3/08
H01L 29/788
Abstract:
Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

Neural Network Classifier Using Array Of Three-Gate Non-Volatile Memory Cells

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US Patent:
20210407588, Dec 30, 2021
Filed:
Sep 9, 2021
Appl. No.:
17/471099
Inventors:
- San Jose CA, US
Steven Lemke - Boulder Creek CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US
Mark Reiten - Alamo CA, US
International Classification:
G11C 11/54
H01L 27/11521
H01L 29/423
G11C 16/04
G06N 3/04
G11C 16/10
G11C 16/14
H01L 29/788
Abstract:
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

Output Circuitry For Non-Volatile Memory Array In Neural Network

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US Patent:
20210287065, Sep 16, 2021
Filed:
Apr 22, 2021
Appl. No.:
17/238077
Inventors:
- San Jose CA, US
- Oakland CA, US
Dmitri Strukov - Goleta CA, US
Nhan Do - Saratoga CA, US
Hieu Van Tran - San Jose CA, US
Vipin Tiwari - Dublin CA, US
Mark Reiten - Alamo CA, US
International Classification:
G06N 3/04
G06N 3/063
G06F 3/06
Abstract:
A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

Precise Data Tuning Method And Apparatus For Analog Neural Memory In An Artificial Neural Network

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US Patent:
20210209456, Jul 8, 2021
Filed:
Mar 25, 2020
Appl. No.:
16/829757
Inventors:
- San Jose CA, US
Steven Lemke - Boulder Creek CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US
Mark Reiten - Alamo CA, US
International Classification:
G06N 3/063
G11C 11/54
G11C 11/56
G06F 17/16
G06F 1/03
Abstract:
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Circuitry To Compensate For Data Drift In Analog Neural Memory In An Artificial Neural Network

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US Patent:
20210209457, Jul 8, 2021
Filed:
Mar 26, 2020
Appl. No.:
16/830733
Inventors:
- San Jose CA, US
STEVEN LEMKE - Boulder Creek CA, US
VIPIN TIWARI - Dublin CA, US
NHAN DO - Saratoga CA, US
MARK REITEN - Alamo CA, US
International Classification:
G06N 3/063
G06F 11/16
G11C 29/44
G11C 13/00
Abstract:
Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.

Precise Data Tuning Method And Apparatus For Analog Neural Memory In An Artificial Neural Network

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US Patent:
20210209458, Jul 8, 2021
Filed:
Feb 25, 2021
Appl. No.:
17/185725
Inventors:
- San Jose CA, US
STEVEN LEMKE - Boulder Creek CA, US
NHAN DO - Saratoga CA, US
MARK REITEN - Alamo CA, US
International Classification:
G06N 3/063
G06F 17/16
Abstract:
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
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Mark William Reiten from Alamo, CA, age ~64 Get Report