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Matthew Banowetz Phones & Addresses

  • 422 W 8Th St, Tipton, IA 52772
  • Hiawatha, IA
  • Ely, IA
  • 1759 E E Ave NE, Cedar Rapids, IA 52402
  • 1104 300Th Ave, Charlotte, IA 52731 (319) 689-6716
  • 1167 310Th Ave, Charlotte, IA 52731
  • Ames, IA
  • 110 N 14Th Ave, Hiawatha, IA 52233

Work

Position: Student

Publications

Us Patents

Track Chain Joint With Radial Seal Unit

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US Patent:
20080231110, Sep 25, 2008
Filed:
Mar 23, 2007
Appl. No.:
11/690215
Inventors:
Patrick John Mulligan - Dubuque IA, US
Matthew Banowetz - Cedar Rapids IA, US
International Classification:
B62D 25/16
US Classification:
305103
Abstract:
An endless track chain device, comprises first and second links and a track chain joint. The track chain joint comprises a radial seal unit that inhibits ingress of debris between a bushing of the joint and the second link into a region between a pin of the joint and the bushing.

System And Method For Power Amplifier Control Saturation Detection And Correction

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US Patent:
20110218020, Sep 8, 2011
Filed:
Mar 3, 2011
Appl. No.:
13/039771
Inventors:
David S. Ripley - Marion IA, US
Paul R. Andrys - Swisher IA, US
Matthew L. Banowetz - Marion IA, US
Assignee:
SKYWORKS SOLUTIONS, INC. - Woburn MA
International Classification:
H04W 52/04
H03G 3/20
H04W 88/02
US Classification:
455571, 330127
Abstract:
A system for power amplifier control saturation detection and correction includes a comparator configured to receive a power control signal and a detected power signal and generate a regulated voltage, a power amplifier configured to receive the regulated voltage and develop an output power, a power detector configured to sense the output power and develop the detected power signal, a saturation detector configured to receive the regulated voltage and a system voltage and determine whether the power amplifier is operating in a saturation mode during a transmit burst, and a current generator configured to reduce the power control signal when the power control signal exceeds a predetermined value and after expiration of a predetermined period of time, preventing the power control signal from exceeding the detected power signal.

Outer Pin Seal

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US Patent:
20120286477, Nov 15, 2012
Filed:
Apr 25, 2008
Appl. No.:
12/597811
Inventors:
Timothy Allen Klousia - Dubuque IA, US
Mark Wayne Stender - Dubuque IA, US
Matthew Edward Banowetz - Cedar Rapids IA, US
Orena Dee Young - Mount Vernon IA, US
Jeffery Frank Olsen - South Jordan UT, US
International Classification:
F16J 15/16
B23P 11/00
US Classification:
277500, 29428
Abstract:
A seal () of substantially wedge shaped cross section self adjusts and seals pivot joints () over a range of gap widths to be sealed.

Internal Serial Interface

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US Patent:
20190272251, Sep 5, 2019
Filed:
Feb 8, 2019
Appl. No.:
16/271441
Inventors:
- Woburn MA, US
Matthew Lee Banowetz - Marion IA, US
International Classification:
G06F 13/42
G06F 13/40
Abstract:
A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.

Wireless Device With Overstress Indicator

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US Patent:
20170374183, Dec 28, 2017
Filed:
Sep 5, 2017
Appl. No.:
15/695086
Inventors:
- Woburn MA, US
Matthew Lee Banowetz - Marion IA, US
Leo John Wilz - Cedar Rapids IA, US
Ali J. Mahmud - Cedar Rapids IA, US
International Classification:
H04M 1/24
H03F 3/19
H03F 1/52
H03F 3/24
Abstract:
According to one aspect, embodiments of the invention provide a wireless device comprising an overstress indicator circuit including a sense circuit configured to monitor a parameter of the wireless device and generate a sense signal corresponding to the parameter, a detection circuit configured to receive the sense signal from the sense circuit and generate a detection signal in response to a determination that the sense signal is indicative of an overstress condition in the device, an interface circuit, and a memory circuit coupled to the detection circuit and the interface circuit and configured to store an overstress condition indication for access via the interface circuit in response to receiving the detection signal, at least one power amplifier coupled to the interface circuit, and a transceiver coupled to the at least one power amplifier and configured to produce an RF transmit signal and to receive an RF receive signal.

Overstress Indicator

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US Patent:
20170187857, Jun 29, 2017
Filed:
Dec 22, 2016
Appl. No.:
15/388273
Inventors:
- Woburn MA, US
Matthew Lee Banowetz - Marion IA, US
Leo John Wilz - Cedar Rapids IA, US
Ali J. Mahmud - Cedar Rapids IA, US
International Classification:
H04M 1/24
G01R 31/28
H03F 1/52
H03F 3/21
H03F 3/19
Abstract:
According to one aspect, embodiments of the invention provide an overstress indicator circuit comprising a sense circuit configured to monitor a parameter of a device and generate a sense signal corresponding to the parameter, a detection circuit coupled to the sense circuit and configured to receive the sense signal from the sense circuit and generate a detection signal at a first level in response to a determination that the sense signal is indicative of an overstress condition in the device, an interface circuit, and a memory circuit coupled to the detection circuit and the interface circuit and configured to store an overstress condition indication for access via the interface circuit in response to receiving the detection signal at the first level.

Linearity Performance For Multi-Mode Power Amplifiers

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US Patent:
20170133987, May 11, 2017
Filed:
Oct 17, 2016
Appl. No.:
15/296007
Inventors:
- Woburn MA, US
Michael Lynn GERARD - Cedar Rapids IA, US
Dwayne Allen ROWLAND - Mayodan NC, US
Matthew Lee BANOWETZ - Marion IA, US
International Classification:
H03F 1/32
H03F 3/24
H03F 3/19
Abstract:
Circuits, devices and methods related to multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.

Internal Serial Interface

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US Patent:
20170091143, Mar 30, 2017
Filed:
Sep 29, 2016
Appl. No.:
15/280768
Inventors:
- Woburn CA, US
Matthew Lee Banowetz - Marion IA, US
International Classification:
G06F 13/42
G06F 13/40
Abstract:
A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.
Matthew E Banowetz from Tipton, IA, age ~48 Get Report