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Michael D Delaus

from Andover, MA
Age ~64
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Also known as:
Mike Delaus
Phone and address:
8 Meadow View Ln, Andover, MA 01810
(978) 749-9645
Related to:
Destiny F Smith, 35Erik C Haas, 56
Connected to:
Barbara A Delauter, 68Edward C Delauter, 36Ethan G Delavan, 53Lien J Delavan, 76Timothy A Delavega, 58Gerard Delavignette, 71Shannon E Delavy, 39Jeannie Delaware, 55Nicole T Delaware, 29Elmer C Delawder, 78

Michael Delaus Phones & Addresses

  • 8 Meadow View Ln, Andover, MA 01810 (978) 749-9645
  • Hartford, VT
  • Atlantic Beach, FL
  • 280 Beacon St, Boston, MA 02116 (617) 375-1009
  • Fairport, NY
  • Penfield, NY
  • Wollaston, MA

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Industries

Semiconductors

Public records

Vehicle Records

Michael Delaus

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Address:
8 Mdw Vw Ln, Andover, MA 01810
Phone:
(978) 749-9645
VIN:
1GNUKKE32AR265551
Make:
CHEVROLET
Model:
SUBURBAN
Year:
2010

Resumes

Resumes

Michael Delaus Photo 1

Michael Delaus

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Location:
Greater Boston Area
Industry:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Michael D. Delaus
Director
ALPHA THETA CHAPTER OF SIGMA CHI FRATERNITY, INC
532 Beacon St, Boston, MA 02215
8 Mdw Vw Ln, Andover, MA 01810

Publications

Us Patents

Thin Film Resistor Fabrication Method

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US Patent:
6426268, Jul 30, 2002
Filed:
Sep 7, 2001
Appl. No.:
09/950219
Inventors:
Gilbert L. Huppert - Stoneham MA
Michael D. Delaus - Andover MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 2120
US Classification:
438384, 438382, 438383, 438385, 438238
Abstract:
A thin film resistor fabrication method requires that an ICs active devices be fabricated on a substrate, and a dielectric layer be deposited over the devices to protect them from subsequent process steps. A layer of thin film material is deposited next, followed by a barrier layer and a first layer of metal. These three layers are patterned and etched to form isolated material stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each TFR. In a preferred embodiment, a dielectric layer is deposited after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length. Once the TFRs are completed, a dielectric layer is preferably deposited, vias to the first layer of metal are patterned and etched, and a second metal layer is deposited, patterned and etched to provide a second layer of metal interconnections.

Laser Trimming With Phase Shifters

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US Patent:
20040207044, Oct 21, 2004
Filed:
Apr 18, 2003
Appl. No.:
10/418535
Inventors:
Paul Ruggerio - Peabody MA, US
David Bain - Castleroberts, IE
Gilbert Huppert - Stoneham MA, US
Edward Gleason - Lexington MA, US
Michael Delaus - Andover MA, US
International Classification:
H01L029/00
US Classification:
257/536000
Abstract:
An improved laser trimming technique allows for a portion of the laser energy to always be on a path length for creating a constructive node independently of the oxide thickness. This improvement is accomplished by forming steps in the reflective silicon that ensure constructive nodes (or prevents the formation of destructive nodes) at the thin film plane. The steps are formed using any of the following techniques: shallow trench isolation, a separate etch step, or LOCOS.

Microphone Package With Embedded Asic

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US Patent:
20120087521, Apr 12, 2012
Filed:
Oct 12, 2011
Appl. No.:
13/272045
Inventors:
Michael D. Delaus - Andover MA, US
Kathy O'Donnell - Arlington MA, US
Thomas M. Goida - Windham NH, US
Assignee:
ANALOG DEVICES, INC. - Norwood MA
International Classification:
H04R 1/00
H01L 21/02
H01L 29/84
US Classification:
381174, 257416, 438 53, 257E29324, 257E21002
Abstract:
A packaged microphone has a base, a lid coupled to the base forming an interior, a MEMS microphone secured to the base within the interior, and an integrated circuit embedded in the base. Apertures in the base and integrated circuit are aligned to form an aperture from the exterior of the package to the interior.

Packaged Microphone With Reduced Parasitics

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US Patent:
20120189144, Jul 26, 2012
Filed:
Jan 24, 2012
Appl. No.:
13/357158
Inventors:
Michael D. Delaus - Andover MA, US
Kathleen O'Donnell - Arlington MA, US
Assignee:
ANALOG DEVICES, INC. - Norwood MA
International Classification:
H04R 1/00
H05K 3/32
US Classification:
381174, 29832
Abstract:
A packaged microphone has a base with a top face, a lid coupled to the base and forming an interior, and a MEMS microphone (i.e., a die or chip) secured to the top face of the base within the interior. The packaged microphone also includes a circuit chip secured to the top face of the base within the interior. The circuit chip has a top surface with a top pad, a bottom surface with a bottom pad, and a via. The bottom pad is electrically connected to the base, and the via electrically connects the top pad with the bottom pad. A wire bond is connected between the MEMS microphone and the top pad on the circuit chip. The MEMS microphone is electrically connected to the bottom pad and the base through the via.

Ic Resistor And Capacitor Fabrication Method

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US Patent:
6365480, Apr 2, 2002
Filed:
Apr 3, 2001
Appl. No.:
09/825386
Inventors:
Gilbert L. Huppert - Stoneham MA
Michael D. Delaus - Andover MA
Edward Gleason - Lexington MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 2120
US Classification:
438381, 438240, 438622, 438706, 438957
Abstract:
An IC resistor and capacitor fabrication method comprises depositing a dielectric layer over existing active devices and metal interconnections on an IC substrate. In a preferred embodiment, a layer of thin film material suitable for the formation of thin film resistors is deposited next, followed by a metal layer that will form the bottom plates of metal-dielectric-metal capacitors. Next, the capacitors dielectric layer is deposited to a desired thickness to target a particular capacitance value, followed by the deposition of another metal layer that will form the capacitors top plates. The metal layers, the capacitor dielectric layer, and the thin film material layer are patterned and etched to form TFRs and metal-dielectric-metal capacitors as desired on the IC substrate. The method may be practiced using any of several alternative process sequences. For example, the bodies of the TFRs can be formed before the deposition of the capacitors layers.

Method Of Transfer Printing

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US Patent:
20210134641, May 6, 2021
Filed:
Feb 17, 2018
Appl. No.:
16/486695
Inventors:
- Hamilton, BM
Susan L. Feindt - Andover MA, US
Michael D. Delaus - Andover MA, US
Matthew Duffy - Wilmington MA, US
Ryan lutzi - Somerville MA, US
Kenneth Flanders - Reading MA, US
International Classification:
H01L 21/683
H01L 25/075
H01L 33/00
H01L 33/32
H01L 33/62
Abstract:
A transfer printing method is described that can be used for a wide variety of materials, such as to allow for circuits formed of different materials to be integrated together on a single integrated circuit. A tether () is formed on dice regions () of a first wafer (), followed by attachment of a second wafer () to the tethers. The dice regions () are processed so as to be separated, followed by transfer printing of the dice regions to a third wafer ().

Low Stress Compact Device Packages

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US Patent:
20160167951, Jun 16, 2016
Filed:
Dec 11, 2014
Appl. No.:
14/567801
Inventors:
- Norwood MA, US
Kathleen O'Donnell - Arlington MA, US
Michael Delaus - Andover MA, US
International Classification:
B81B 7/00
H01L 25/18
H01L 23/498
B81C 1/00
Abstract:
Various low stress compact device packages are disclosed herein. An integrated device package can include a first integrated device die and a second integrated device die. An interposer can be disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer. The first side can be opposite the second side. The interposer can comprise a hole through at least the second side of the interposer. A portion of the second integrated device die can extend into the hole.
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Michael D Delaus from Andover, MA, age ~64 Get Report