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Narain K Vijayashanker

from San Jose, CA
Age ~35
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Also known as:
Narain Kumar Vijayashanker
Related to:
Nirmala VijayashankerVijay Rajagopalan, 51Bijay Rajagopalan, 70Poornima Vijayashanker, 41V Rajagopalan, 70Vijayasha Rajagopalan, 70
Connected to:
Athulan Vijayaraghavan, 40Janaki Vijayaragavan, 42Bharath A Vijayendra, 57Jan Vijg, 70Ana T Vijil, 82Carolyn R Vik, 53Linda M Vik, 63Michael P Vik, 61Rune Vik, 59Spencer Vik

Narain Vijayashanker Phones & Addresses

  • San Jose, CA
  • 965 Mangrove Ave APT 11, Sunnyvale, CA 94086
  • Palo Alto, CA
  • Fairview, OR

Work

Company: Synaptics Aug 2013 Address: San Jose, CA Position: Sr. systems design engineer

Education

Degree: B.S. School / High School: California Institute of Technology 2006 to 2010 Specialities: Electrical Engineering

Skills

Semiconductors • Labview • Asic • Pcb Design • Matlab • Integrated Circuit Design • Comsol • Ansys • Maxwell • Finite Element Analysis • Python • Network Analyzer • Rapid Prototyping • Amperes 3D • Solidworks • Spice • Laser Cutting • Cadence Virtuoso • Cadence Spectre • Verilog Ams • Functional Verification • System Architecture • Application Specific Integrated Circuits • Algorithms • C • Embedded Systems • Simulations • Sensors • Verilog • Verification and Validation • Latex

Languages

English • Tamil

Ranks

Certificate: Electronic Circuits Graduate Certificate

Industries

Semiconductors

Resumes

Resumes

Narain Vijayashanker Photo 1

Staff Analog Hardware Engineer

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Location:
1409 Hervey Ln, San Jose, CA 95125
Industry:
Semiconductors
Work:
Synaptics - San Jose, CA since Aug 2013
Sr. Systems Design Engineer
Synaptics - San Jose, CA Nov 2010 - Aug 2013
System Design Engineer
Synaptics - San Jose, CA Jun 2010 - Nov 2010
IC Design Intern
Education:
California Institute of Technology 2006 - 2010
B.S., Electrical Engineering
Skills:
Semiconductors
Labview
Asic
Pcb Design
Matlab
Integrated Circuit Design
Comsol
Ansys
Maxwell
Finite Element Analysis
Python
Network Analyzer
Rapid Prototyping
Amperes 3D
Solidworks
Spice
Laser Cutting
Cadence Virtuoso
Cadence Spectre
Verilog Ams
Functional Verification
System Architecture
Application Specific Integrated Circuits
Algorithms
C
Embedded Systems
Simulations
Sensors
Verilog
Verification and Validation
Latex
Languages:
English
Tamil
Certifications:
Electronic Circuits Graduate Certificate
Stanford University

Publications

Us Patents

Input Device With Integrated Deformable Electrode Structure For Force Sensing

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US Patent:
20130068038, Mar 21, 2013
Filed:
Sep 21, 2011
Appl. No.:
13/238783
Inventors:
Robert James Bolender - Santa Clara CA, US
Narain Kumar Vijayashanker - Palo Alto CA, US
Joseph Kurth Reynolds - Alviso CA, US
Lin-Hsiang Hsieh - Taoyuan City, TW
Shwetank Kumar - Sunnyvale CA, US
Assignee:
SYNAPTICS INCORPORATED - Santa Clara CA
International Classification:
G01L 1/00
US Classification:
73862626
Abstract:
Devices and methods are provided that facilitate improved input device performance. The devices and methods utilize a first electrode and a second electrode disposed on a first substrate and a deformable electrode structure. The deformable electrode structure overlaps the first electrode and the second electrode to define a variable capacitance between the first electrode and the second electrode that changes with the deformation of the deformable electrode structure. The deformable electrode structure comprises a spacing component configured to provide spacing between the deformable electrode structure and the first electrode and the second electrode. Finally, a transmission component is configured such that biasing the transmission component causes the deformable electrode structure to deform and change the variable capacitance. A measurement of the variable capacitance can be used to determine force information regarding the force biasing the transmission component.
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Narain K Vijayashanker from San Jose, CA, age ~35 Get Report