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Otto Sperber Phones & Addresses

  • 35729 32Nd Ave, Phoenix, AZ 85086 (623) 388-3260
  • Anthem, AZ
  • 6051 Point Loma Dr, Huntington Beach, CA 92647 (714) 842-3920 (714) 847-2783
  • Rochester, NY
  • La Jolla, CA

Publications

Us Patents

Method Of Addressing Devices And Transferring Data On A Bus

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US Patent:
52934950, Mar 8, 1994
Filed:
Jun 29, 1992
Appl. No.:
7/907756
Inventors:
Uoc H. Nguyen - Long Beach CA
George L. Eldridge - Long Beach CA
Otto Sperber - Huntington Beach CA
Assignee:
Xerox Corporation - Stamford CT
International Classification:
G06F 1338
US Classification:
395325
Abstract:
A method is described for transferring data on a digital data bus system. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. A bus controller is connected to the bus. A plurality of devices are also connected to the bus. Each device has a predetermined address. The control lines include a bus grant line for communicating a bus grant signal that permits the devices addressed by the bus controller to send or receive data signals. According to the method, the bus controller generates a bus grant signal on the bus grant line and source address and destination address signals on the address lines. The devices receive the bus grant signal and the source address and destination address signals. The devices decode the source address and destination address signals in response to the bus grant signal.

Streaming Memory Controller For A Pci Bus

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US Patent:
61638188, Dec 19, 2000
Filed:
Aug 27, 1998
Appl. No.:
9/141398
Inventors:
Uoc H. Nguyen - Long Beach CA
Otto Sperber - Huntington Beach CA
Khanh Q. Tran - Irvine CA
David K. Bovaird - West Hills CA
Assignee:
Xerox Corporation - Stamford CT
International Classification:
G06F 1300
US Classification:
710 22
Abstract:
In a system having a PCI bus, an additional memory attached to the bus to allow a higher speed of data transfer for a number of copies from the computer to a number of devices. The additional memory has a number of DMA channels, each associated with an I/O device. One copy of the data required by an I/O device is transferred to the memory at normal computer FIFO speed. Thereafter, multiple copies of that data can be transferred to the I/O device from the memory at the higher data bus speed.
Otto L Sperber from Phoenix, AZ, age ~78 Get Report